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Bit 0
MODEN
This bit enables the I2C operations.
1 (R/W): Enable I2C operations (The operating clock is supplied.)
0 (R/W): Disable I2C operations (The operating clock is stopped.)
Note:
If the I2C_nCTL.MODEN bit is altered from 1 to 0 while sending/receiving data, the data being
sent/received cannot be guaranteed. When setting the I2C_nCTL.MODEN bit to 1 again after that,
be sure to write 1 to the I2C_nCTL.SFTRST bit as well.
I2C Ch.n Transmit Data Register
Register name
Bit
I2C_nTXD
15–8
7–0
Bits 15–8
Reserved
Bits 7–0
TXD[7:0]
Data can be written to the transmit data buffer through these bits. Make sure the
I2C_nINTF.TBEIF bit is set to 1 before writing data.
Note:
Be sure to avoid writing to the I2C_nTXD register when the I2C_nINTF.TBEIF bit = 0, otherwise
transmit data cannot be guaranteed.
I2C Ch.n Receive Data Register
Register name
Bit
I2C_nRXD
15–8
7–0
Bits 15–8
Reserved
Bits 7–0
RXD[7:0]
The receive data buffer can be read through these bits.
I2C Ch.n Status and Interrupt Flag Register
Register name
Bit
I2C_nINTF
15–13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bits 15–13 Reserved
Bit 12
SDALOW
This bit indicates that SDA is set to low level.
1 (R): SDA = Low level
0 (R): SDA = High level
16-24
Bit name
Initial
Reset
–
0x00
TXD[7:0]
0x00
Bit name
Initial
Reset
–
0x00
RXD[7:0]
0x00
Bit name
Initial
–
0x0
SDALOW
0
SCLLOW
0
BSY
0
TR
0
–
0
BYTEENDIF
0
GCIF
0
NACKIF
0
STOPIF
0
STARTIF
0
ERRIF
0
RBFIF
0
TBEIF
0
Seiko Epson Corporation
R/W
–
R
H0
R/W
R/W
–
R
H0
R
Reset
R/W
–
R
–
H0
R
H0
R
H0/S0
R
H0
R
–
R
H0/S0
R/W
Cleared by writing 1.
H0/S0
R/W
H0/S0
R/W
H0/S0
R/W
H0/S0
R/W
H0/S0
R/W
H0/S0
R
Cleared by reading the I2C_nRXD
register.
H0/S0
R
Cleared by writing to the I2C_nTXD
register.
S1C31D50 TECHNICAL MANUAL
Remarks
–
Remarks
–
Remarks
(Rev. 1.00)
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