Epson S1C17W14 Technical Manual
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Epson S1C17W14 Technical Manual

Epson S1C17W14 Technical Manual

Cmos 16-bit single chip microcontroller
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CMOS 16-BIT SINGLE CHIP MICROCONTROLLER
S1C17W14/W16
Technical Manual
Rev. 1.2

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Summary of Contents for Epson S1C17W14

  • Page 1 CMOS 16-BIT SINGLE CHIP MICROCONTROLLER S1C17W14/W16 Technical Manual Rev. 1.2...
  • Page 2 2. This evaluation board/kit or development tool is intended for use by an electronic engineer and is not a consumer product. The user should use it properly and in a safe manner. Seiko Epson does not assume any responsibility or liability of any kind of damage and/or fire caused by its use.

  • Page 3: Notational Conventions And Symbols In This Manual

    PREFACE Preface This is a technical manual for designers and programmers who develop a product using the S1C17W14/W16. This document describes the functions of the IC, embedded peripheral circuit operations, and their control methods. For the CPU functions and instructions, refer to the “S1C17 Family S1C17 Core Manual.” For the functions and operations of the debugging tools, refer to the respective tool manuals.

  • Page 4: Table Of Contents

    3.2 CPU Core ........................3-2 3.2.1 CPU Registers ....................3-2 3.2.2 Instruction Set ....................3-2 3.2.3 Reading PSR ....................3-2 3.2.4 I/O Area Reserved for the S1C17 Core ............3-2 3.3 Debugger ........................3-2 Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)
  • Page 5 6.2.4 CMOS Output and High Impedance State ............6-3 6.3 Clock Settings ......................... 6-3 6.3.1 PPORT Operating Clock ................... 6-3 6.3.2 Clock Supply in SLEEP Mode ................6-3 6.3.3 Clock Supply in DEBUG Mode ................. 6-3 Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)
  • Page 6 9.3.2 Theoretical Regulation Function ............... 9-2 9.4 Operations ........................9-3 9.4.1 RTCA Control ....................9-3 9.4.2 Real-Time Clock Counter Operations ............... 9-4 9.4.3 Stopwatch Control .................... 9-4 9.4.4 Stopwatch Count-up Pattern ................9-4 9.5 Interrupts ......................... 9-5 Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)
  • Page 7 T16 Ch.n Mode Register ......................11-5 T16 Ch.n Control Register ......................11-5 T16 Ch.n Reload Data Register ....................11-6 T16 Ch.n Counter Data Register ....................11-6 T16 Ch.n Interrupt Flag Register ....................11-6 Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)
  • Page 8 13.5.3 Data Reception in Master Mode ..............13-7 13.5.4 Terminating Data Transfer in Master Mode ............ 13-8 13.5.5 Data Transfer in Slave Mode ................13-8 13.5.6 Terminating Data Transfer in Slave Mode ............. 13-10 Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)
  • Page 9 15.4 Operations ........................15-4 15.4.1 Initialization ....................15-4 15.4.2 Counter Block Operations ................15-5 15.4.3 Comparator/Capture Block Operations ............15-8 15.4.4 TOUT Output Control ................... 15-16 15.5 Interrupt ........................15-22 15.6 Control Registers ......................15-22 Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)
  • Page 10 17.7 Control Registers ......................17-7 REMC2 Clock Control Register ....................17-7 REMC2 Data Bit Counter Control Register ................17-8 REMC2 Data Bit Counter Register ................... 17-9 REMC2 Data Bit Active Pulse Length Register ............... 17-10 Seiko Epson Corporation viii S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)
  • Page 11 19.2 Input/Output Pins and External Connections .............. 19-2 19.2.1 List of Input/Output Pins ................19-2 19.2.2 External Connections ..................19-2 19.3 Clock Settings ......................19-3 19.3.1 RFC Operating Clock ..................19-3 19.3.2 Clock Supply in SLEEP Mode ............... 19-3 Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)
  • Page 12 22.1 Absolute Maximum Ratings ..................22-1 22.2 Recommended Operating Conditions ................. 22-1 22.3 Current Consumption ....................22-2 22.4 System Reset Controller (SRC) Characteristics ............22-4 22.5 Clock Generator (CLG) Characteristics................ 22-4 22.6 Flash Memory Characteristics ..................22-7 Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)
  • Page 13 B.1 Operating Status Configuration Examples for Power Saving ........AP-B-1 B.2 Other Power Saving Methods ..................AP-B-2 Appendix C Mounting Precautions ................AP-C-1 Appendix D Measures Against Noise ................ AP-D-1 Appendix E Initialization Routine ................AP-E-1 Revision History Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 14: Overview

    1 OVERVIEW 1 Overview The S1C17W14/W16 is a 16-bit MCU that features low-voltage operation from 1.2 V even though Flash memory is included. The embedded high-efficiency DC-DC converter generates the constant-voltage to drive the IC with lower power consumption than 4-bit MCUs. This IC includes a real-time clock, a stopwatch, an LCD driver, and a PWM timer capable of being used to generate drive waveforms for a motor driver as well as a high-performance 16-bit CPU.
  • Page 15 OSC1 = 32 kHz, RTC = ON, super economy mode RUN mode 6 µA OSC1 = 32 kHz, RTC = ON, CPU = OSC1 3 µA OSC1 = 32 kHz, RTC = ON, CPU = OSC1, super economy mode Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 16: Block Diagram

    3 Ch. Sound generator BZOUT (SNDA) #BZOUT TOUT00–01 TOUT10–11 16-bit PWM timer IR remote CAP00–01 (T16B) controller CAP10–11 REMO 2 Ch. (REMC2) EXCL00–01 CLPLS 1 Ch. EXCL10–11 Figure 1.2.1 S1C17W14 Block Diagram Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)
  • Page 17 16-bit PWM timer IR remote CAP00–01 (T16B) controller CAP10–11 REMO 2 Ch. (REMC2) EXCL00–01 CLPLS 1 Ch. EXCL10–11 12-bit A/D ADIN00–03 converter VREFA0 (ADC12A) #ADTRG0 1 Ch. Figure 1.2.2 S1C17W16 Block Diagram Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 18: Pins

    P01/SENA0/UPMUX P00/SENB0/UPMUX SEG25 SEG25 SEG24 DCLK/PD2 SEG24 SEG23 SEG23 DSIO/PD1 SEG22 SEG22 DST2/PD0 SEG21 SEG21 COM0 COM0 SEG20 SEG20 COM1 COM1 N.C. N.C. COM2 COM2 Figure 1.3.1.1 S1C17W14 Pin Configuration Diagram (QFP15-100PIN) Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)
  • Page 19 SEG26 SEG26 DCLK/PD2 SEG25 SEG25 DSIO/PD1 SEG24 SEG24 N.C. N.C. N.C. N.C. DST2/PD0 SEG23 SEG23 COM0 COM0 COM1 COM1 COM2 COM2 N.C. N.C. N.C. N.C. Figure 1.3.1.2 S1C17W16 Pin Configuration Diagram (TQFP15-128PIN) Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 20: Pad Configuration Diagram (Chip)

    P42/SEG43 Die No. CJxxxxxxx P43/SEG42 2.435 mm Figure 1.3.2.1 S1C17W14 Pad Configuration Diagram (Chip) Pad opening No. 1–25, 51–73: X = 68 µm, Y = 80 µm No. 26–50, 74–96: X = 80 µm, Y = 68 µm Chip thickness 400 µm...
  • Page 21 1 OVERVIEW Table 1.3.2.1 S1C17W14 Pad Coordinates X µm Y µm X µm Y µm X µm Y µm X µm Y µm -1,049.5 -1,114.5 1,132.0 -856.0 915.9 1,114.5 -1,132.0 951.8 -969.5 -1,114.5 1,132.0 -776.0 835.9 1,114.5 -1,132.0 871.8 -889.5 -1,114.5 1,132.0...
  • Page 22 Figure 1.3.2.2 S1C17W16 Pad Configuration Diagram (Chip) Pad opening No. 1–28, 55–81: X = 68 µm, Y = 80 µm No. 29–54, 82–108: X = 80 µm, Y = 68 µm Chip thickness 400 µm Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 23: Pin Descriptions

    DC-DC converter stabilization capacitor connect pin ✓ ✓ – – DC-DC converter charge pump capacitor connect pins ✓ ✓ V1–2 V1–2 – – LCD panel driver power supply ✓ ✓ C1–3 C1–3 Seiko Epson Corporation 1-10 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)
  • Page 24 12-bit A/D converter Ch.0 reference voltage input – ✓ Hi-Z – I/O port – ✓ UPMUX User-selected I/O (universal port multiplexer) – ✓ ADIN00 12-bit A/D converter Ch.0 analog signal input 0 – ✓ Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL 1-11 (Rev. 1.2)
  • Page 25 LCD common output – ✓ Hi-Z I/O port ✓ ✓ ✓ REF1 R/F converter Ch.1 reference oscillator pin – ✓ SEG43 LCD segment output ✓ – SEG49 LCD common output – ✓ Seiko Epson Corporation 1-12 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)
  • Page 26 Table 1.3.3.2 Peripheral Circuit Input/output Function Selectable by UPMUX Peripheral circuit Signal to be assigned Channel number n Function Synchronous serial SDIn S1C17W14: n = 0, 1 SPIA Ch.n data input interface S1C17W16: n = 0, 1, 2 SDOn SPIA Ch.n data output (SPIA) SPICLKn SPIA Ch.n clock input/output...

  • Page 27: Power Supply, Reset, And Clocks

    Power supply voltage V ” in the “Electrical Characteristics” chapter and the “Basic External Connection Diagram” chapter, respectively. Note: Be sure to avoid using the V and V pin outputs for driving external circuits. Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 28: Operations

    PWGINTF.MODCMPIF bit to 1. 2. When a clock source other than OSC1 is started in economy mode The hardware switches to normal mode at the same time the clock source is started. Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)
  • Page 29 (or economy mode). Do not perform heavy- load operations, such as starting a high-speed clock source, before the PWGINTF.MODC- MPIF bit is set to 1, as it may cause a malfunction. Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 30: System Reset Controller (Src)

    The reset source refers to causes that request system initialization. The following shows the reset sources. #RESET pin Inputting a reset signal with a certain low level period to the #RESET pin issues a reset request. Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 31: Initialization Conditions (Reset Groups)

    Watchdog timer reset #RESET pin Peripheral circuit software reset Reset state is canceled immediately (MODEN and SFTRST bits. The after the reset request is canceled. software reset operations de- pend on the peripheral circuit. Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 32: Clock Generator (Clg)

    OSC4 EXOSCEN EXOSC EXOSC EXOSCCLK clock input circuit FOUTEN Peripheral circuit 1 FOUT FOUT Clock output CLKSRC[x:0] selector circuit CLKDIV[x:0] FOUTDIV[2:0] Peripheral circuit n Clock CLKSRC[x:0] selector CLKDIV[x:0] Figure 2.3.1.1 CLG Configuration Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 33: Input/Output Pins

    OSC1 oscillator circuit The OSC1 oscillator circuit is a high-precision and low-power oscillator circuit that uses a 32.768 kHz crystal resonator. Figure 2.3.3.2 shows the configuration of the OSC1 oscillator circuit. Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)
  • Page 34 OSC3 and OSC4 pins may affect the oscillation frequency. • When the internal oscillator is selected, be sure to avoid using the pins to which OSC3 and OSC4 are assigned as input pins, as it may affect the oscillation frequency. Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 35: Operations

    Figure 2.3.4.1 shows the relationship be- tween the oscillation start time and the oscillation stabilization waiting time. Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)
  • Page 36 Oscillator circuit enable (CLGOSC.OSC1EN) Oscillation inverter INV1B[1:0] setting gain INV1N[1:0] setting gain Oscillation waveform Startup boosting Normal operation operation Figure 2.3.4.2 Operation Example when the Oscillation Startup Control Circuit is Used Seiko Epson Corporation 2-10 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)
  • Page 37 Note: Make sure the CLGOSC.OSC3EN bit is set to 0 (while the OSC3 oscillation is halted) when switching the oscillator within three types. Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL 2-11 (Rev. 1.2)
  • Page 38 CLGSCLK.CLKSRC[1:0] = 0x0 (IOSC) CLGSCLK.WUPSRC[1:0] = 0x0 (IOSC) CLGSCLK.WUPSRC[1:0] = 0x0 (IOSC) ∗ Switching to IOSC that features fast initiation allows high-speed processing. Figure 2.3.4.4 Clock Control Example at SLEEP Cancelation Seiko Epson Corporation 2-12 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)
  • Page 39 7. The OSC1 oscillation stops if the CLGINTF.OSC1STPIF bit = 1 after an interrupt occurs. If the CLGOSC1.OSDRB bit = 1, the hardware restarts the OSC1 oscillator circuit. Note: Enabling the oscillation stop detection function increase the oscillation stop detector current OSD1 Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL 2-13 (Rev. 1.2)

  • Page 40: Operating Mode

    When a debug interrupt occurs, the CPU enters DEBUG mode. DEBUG mode is canceled when the retd in- struction is executed. For more information on DEBUG mode, refer to “Debugger” in the “CPU and Debugger” chapter. Seiko Epson Corporation 2-14 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)
  • Page 41 CPU into RUN mode. This transition is executed even if the CPU does not accept the interrupt request. • Interrupt request from a peripheral circuit • NMI • Debug interrupt • Reset request Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL 2-15 (Rev. 1.2)

  • Page 42: Interrupts

    Operating mode 0x7–0x6 Reserved Super economy mode Reserved Economy mode Normal mode Reserved Automatic mode Note: The PWGCTL.PWGMOD[2:0] bits are set to 0x0 when 0x7, 0x6, 0x4, or 0x1 is written. Seiko Epson Corporation 2-16 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 43: Pwg2 Timing Control Register

    Bit name Initial Reset Remarks CLGSCLK WUPMD R/WP – – – 13–12 WUPDIV[1:0] R/WP 11–10 – – 9–8 WUPSRC[1:0] R/WP 7–6 – – 5–4 CLKDIV[1:0] R/WP 3–2 – – 1–0 CLKSRC[1:0] R/WP Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL 2-17 (Rev. 1.2)
  • Page 44 When a currently stopped clock source is selected, it will automatically start oscillating or clock input. Table 2.6.4 SYSCLK Clock Source and Division Ratio Settings CLGSCLK.CLKSRC[1:0] bits CLGSCLK. CLKDIV[1:0] bits IOSCCLK OSC1CLK OSC3CLK EXOSCCLK Reserved 1/16 Reserved Reserved Reserved Reserved Seiko Epson Corporation 2-18 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 45: Clg Oscillation Control Register

    IOSC oscillator circuit CLG IOSC Control Register Register name Bit name Initial Reset Remarks CLGIOSC 15–8 – 0x00 – – 7–5 – – IOSCSTM R/WP 3–0 – – Bits 15–5 Reserved Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL 2-19 (Rev. 1.2)

  • Page 46: Clg Osc1 Control Register

    0. Bit 12 OSC1BUP This bit enables the oscillation startup control circuit in the OSC1 oscillator circuit. 1 (R/WP): Enable (Activate booster operation at startup.) 0 (R/WP): Disable Bit 11 Reserved Seiko Epson Corporation 2-20 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 47: Clg Osc3 Control Register

    CLG OSC3 Control Register Register name Bit name Initial Reset Remarks CLGOSC3 15–13 – – – 12–10 OSC3FQ[2:0] R/WP 9–8 OSC3MD[1:0] R/WP 7–6 – – 5–4 OSC3INV[1:0] R/WP – – 2–0 OSC3WT[2:0] R/WP Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL 2-21 (Rev. 1.2)
  • Page 48 These bits set the oscillation stabilization waiting time for the OSC3 oscillator circuit. Table 2.6.12 OSC3 Oscillation Stabilization Waiting Time Setting CLGOSC3.OSC3WT[2:0] bits Oscillation stabilization waiting time 65,536 clocks 16,384 clocks 4,096 clocks 1,024 clocks 256 clocks 64 clocks 16 clocks 4 clocks Seiko Epson Corporation 2-22 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 49: Clg Interrupt Flag Register

    Note: The CLGINTF.IOSCSTAIF bit is 0 after system reset is canceled, but IOSCCLK has already been stabilized. CLG Interrupt Enable Register Register name Bit name Initial Reset Remarks CLGINTE 15–8 – 0x00 – – – – (reserved) OSC1STPIE IOSCTEDIE – – OSC3STAIE OSC1STAIE IOSCSTAIE Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL 2-23 (Rev. 1.2)

  • Page 50: Clg Fout Control Register

    1/256 1/16 Reserved Reserved Reserved Reserved Note: When the CLGFOUT.FOUTSRC[1:0] bits are set to 0x3, the FOUT output will be stopped in SLEEP/HALT mode as SYSCLK is stopped. Bit 1 Reserved Seiko Epson Corporation 2-24 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)
  • Page 51 0 (R/W): Disable external output Note: Since the FOUT signal generated is out of sync with writings to the CLGFOUT.FOUTEN bit, a glitch may occur when the FOUT output is enabled or disabled. Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL 2-25 (Rev. 1.2)

  • Page 52: Cpu And Debugger

    3 CPU AND DEBUGGER 3 CPU and Debugger 3.1 Overview This IC incorporates the Seiko Epson original 16-bit CPU core (S1C17) with a debugger. The main features of the CPU core are listed below. • Seiko Epson original 16-bit RISC processor...

  • Page 53: Cpu Core

    Debugging requires a 64-byte debugging work area. For more information on the work area location, refer to the “Memory and Bus” chapter. The start address of this debugging work area can be read from the DBRAM register. Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 54: List Of Debugger Input/Output Pins

    For the recommended pull-up resistor value, refer to “Recommended Operating Conditions, DSIO pull-up resis- tor R ” in the “Electrical Characteristics” chapter. R is not required when using the DSIO pin as a general- purpose I/O port pin. Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 55: Flash Security Function

    The value (0 or 1) of the PSR Z (zero) flag can be read out with this bit. Bit 0 PSRN The value (0 or 1) of the PSR N (negative) flag can be read out with this bit. Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 56: Debug Ram Base Register

    – 23–0 DBRAM[23:0] *1 Debugging work area start address Bits 31–24 Reserved Bits 23–0 DBRAM[23:0] The start address of the debugging work area (64 bytes) can be read out with these bits. Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 57: Memory And Bus

    Debug RAM area (64 bytes) RAM area 0x00 0fc0 0x00 0fbf (8K bytes) RAM area (Device size: 32 bits) (4K bytes) (Device size: 32 bits) 0x00 0000 0x00 0000 Figure 4.1.1 Memory Map Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 58: Bus Access Cycle

    For the V voltage, refer to “Recommended Operating Conditions, Flash programming voltage V ” in the “Elec- trical Characteristics” chapter. Note: Always leave the V pin open except when programming the Flash memory. Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 59: Flash Bus Access Cycle Setting

    The control registers for the peripheral circuits are located in the 8K-byte area beginning with address 0x4000. Table 4.6.1 shows the control register map. For details of each control register, refer to “List of Peripheral Circuit Registers” in the appendix or “Control Registers” in each peripheral circuit chapter. Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)
  • Page 60 P0 Port Enable Register 0x4204 P0RCTL P0 Port Pull-up/down Control Register 0x4206 P0INTF P0 Port Interrupt Flag Register 0x4208 P0INTCTL P0 Port Interrupt Control Register 0x420a P0CHATEN P0 Port Chattering Filter Enable Register Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)
  • Page 61 P36–37 Universal Port Multiplexer Setting Register UART (UART) Ch.0 0x4380 UA0CLK UART Ch.0 Clock Control Register 0x4382 UA0MOD UART Ch.0 Mode Register 0x4384 UA0BR UART Ch.0 Baud-Rate Register 0x4386 UA0CTL UART Ch.0 Control Register Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)
  • Page 62 UART Ch.1 Interrupt Enable Register 16-bit timer (T16) Ch.2 0x5260 T16_2CLK T16 Ch.2 Clock Control Register 0x5262 T16_2MOD T16 Ch.2 Mode Register 0x5264 T16_2CTL T16 Ch.2 Control Register 0x5266 T16_2TR T16 Ch.2 Reload Data Register Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)
  • Page 63 RFC Ch.1 Control Register * 0x5462 RFC1CTL RFC Ch.1 Oscillation Trigger Register * 0x5464 RFC1TRG RFC Ch.1 Measurement Counter Low Register * 0x5466 RFC1MCL RFC Ch.1 Measurement Counter High Register * 0x5468 RFC1MCH Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 64: System-Protect Function

    MISC IRAM Size Register Register name Bit name Initial Reset Remarks MSCIRAMSZ 15–9 – 0x00 – – (reserved) R/WP Always set to 0. 7–3 – 0x06 – – 2–0 IRAMSZ[2:0] R/WP Bits 15–3 Reserved Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 65: Flashc Flash Read Cycle Register

    FLASHCWAIT.RDWAIT[1:0] bits Number of bus Access cycles System clock frequency 4.2 MHz (max.) 4.2 MHz (max.) 4.2 MHz (max.) 2.1 MHz (max.) Note: Be sure to set the FLASHCWAIT.RDWAIT[1:0] bits before the system clock is configured. Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 66: Interrupt Controller (Itc)

    TTBR + 0x04 Address misaligned interrupt Memory access instruction – (0xfffc00) Debugging interrupt brk instruction, etc. 2 (0x02) TTBR + 0x08 – 3 (0x03) TTBR + 0x0c Reserved for C compiler – – Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)
  • Page 67 (S1C17W16 only) • Sensor A oscillation completion • Sensor B oscillation completion • Measurement counter overflow error • Time base counter overflow error 22 (0x16) TTBR + 0x58 16-bit timer Ch.2 interrupt Underflow Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 68: Vector Table Base Address (Ttbr)

    ITC even if the interrupt flag is set to 1. An interrupt request is also sent to the ITC if the status is changed to interrupt enabled when the interrupt flag is 1. Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 69: Itc Interrupt Request Processing

    (0–7) to be set to the IL[2:0] bits in the PSR. The software inter- rupt cannot be disabled (non-maskable interrupt). The processor performs the same interrupt processing operation as that of the hardware interrupt. Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 70: Interrupt Processing By The Cpu

    – 2–0 ILVy [2:0] Bits 15–11 Reserved Bits 7–3 Reserved = 2x +1) Bits 10–8 ILVy [2:0] = 2x) Bits 2–0 ILVy [2:0] These bits set the interrupt level of each interrupt. Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)
  • Page 71 15–11 – 0x00 – – (ITC Interrupt Level 10–8 ILV17[2:0] R/F converter Ch.1 interrupt Setup Register 8) (ILVRFC_1) (S1C17W16 only) 7–3 – 0x00 – – 2–0 ILV16[2:0] R/F converter Ch.0 interrupt (ILVRFC_0) Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)
  • Page 72 – (ITC Interrupt Level 10–8 ILV23[2:0] Synchronous serial interface Ch.2 in- Setup Register 11) terrupt (ILVSPIA_2) (S1C17W16 only) 7–3 – 0x00 – – 2–0 ILV22[2:0] 16-bit timer Ch.4 interrupt (ILVT16_4) (S1C17W16 only) Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 73: O Ports (Pport)

    Note: ‘x’, which is used in the port names Pxy, register names, and bit names, refers to a port group (x = 0, 1, 2, ··· , d) and ‘y’ refers to a port number (y = 0, 1, 2, ··· , 7). Figure 6.1.1 shows the configuration of PPORT. Table 6.1.1 Port Configuration of S1C17W14/W16 Item S1C17W14...

  • Page 74: I/O Cell Structure And Functions

    Falling time (port level = high → low) [second] High level Schmitt input threshold voltage [V] Low level Schmitt input threshold voltage [V] : Pull-up/pull-down resistance [W] Pin capacitance [F] Parasitic capacitance on the board [F] BOARD Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 75: Cmos Output And High Impedance State

    • Port pins: High impedance state • Port function: Configured to GPIO This status continues until the ports are configured via software. The debugging function ports are configured for debug signal input/output. Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)
  • Page 76 * Steps 1 and 5 are required for the ports with an interrupt function. Step 2 is required for the ports with a chat- tering filter function. Table 6.4.1.1 lists the port status according to the combination of data input/output control and pull-up/down control. Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 77: Port Input/Output Control

    1. Configure the ports to be used for key-entry reset as general-purpose input ports (refer to “Initial settings when using a port as a general-purpose input port (only for the ports with GPIO function)”). 2. Configure the input pin combination for key-entry reset using the PCLK.KRSTCFG[1:0] bits. Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 78: Interrupts

    These bits are used to set data to be output from the GPIO port pins. 1 (R/W): Output high level from the port pin 0 (R/W): Output low level from the port pin Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 79: Px Port Enable Register

    PxIOEN.PxIENy bit is set and the port is not pulled up/down. These bits do not affect the pull-up/down control when the port is used as a peripheral I/O function. Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 80: Px Port Interrupt Flag Register

    PxMODSEL 15–8 – 0x00 – – 7–0 PxSEL[7:0] 0x00 *1: The bit configuration differs depending on the port group. *2: The initial value may be changed by the port. Bits 15–8 Reserved Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 81: Px Port Function Select Register

    Table 6.6.2 Key-Entry Reset Function Settings PCLK.KRSTCFG[1:0] bits key-entry reset Reset when P0[3:0] inputs = all low Reset when P0[2:0] inputs = all low Reset when P0[1:0] inputs = all low Disable Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 82: P Port Interrupt Flag Group Register

    A port generated an interrupt 0 (R): No port generated an interrupt The PINTFGRP.PxINT bit is cleared when the interrupt flag for the port that has generated an interrupt is cleared. Seiko Epson Corporation 6-10 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 83: Control Register And Port Function Configuration Of This Ic

    This section shows the PPORT control register/bit configuration in this IC and the list of peripheral I/O functions selectable for each port. 6.7.1 P0 Port Group The P0 port group supports the GPIO and interrupt functions. Table 6.7.1.1 Control Registers for P0 Port Group (S1C17W14/W16) Register name Bit name Initial...

  • Page 84: P1 Port Group

    6 I/O PORTS (PPORT) 6.7.2 P1 Port Group The P1 port group supports the GPIO and interrupt functions. Table 6.7.2.1 Control Registers for P1 Port Group (S1C17W14/W16) Register name Bit name Initial Reset Remarks P1DAT 15–8 P1OUT[7:0] 0x00 – (P1 Port Data 7–0 P1IN[7:0]...

  • Page 85: P2 Port Group

    – – – – UPMUX ADC12A ADIN01 – – – – UPMUX ADC12A ADIN02 – – – – UPMUX ADC12A ADIN03 – – *1: Refer to the “Universal Port Multiplexer” chapter. Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL 6-13 (Rev. 1.2)

  • Page 86: P3 Port Group

    6 I/O PORTS (PPORT) 6.7.4 P3 Port Group The P3 port group supports the GPIO and interrupt functions. Table 6.7.4.1 Control Registers for P3 Port Group (S1C17W14/W16) Register name Bit name Initial Reset Remarks P3DAT 15–8 P3OUT[7:0] 0x00 – (P3 Port Data 7–0 P3IN[7:0]...

  • Page 87: P4 Port Group

    6 I/O PORTS (PPORT) 6.7.5 P4 Port Group The P4 port group consists of four ports P40–P43 (S1C17W14) or five ports P40–P44 (S1C17W16) and they sup- port the GPIO and interrupt functions. Table 6.7.5.1 Control Registers for P4 Port Group (S1C17W14)
  • Page 88 9–8 P44MUX[1:0] Select Register) 7–6 P43MUX[1:0] S1C17W16 5–4 P42MUX[1:0] 3–2 P41MUX[1:0] 1–0 P40MUX[1:0] Table 6.7.5.3 P4 Port Group Function Assignment (S1C17W14) P4SELy = 0 P4SELy = 1 Port P4yMUX = 0x0 P4yMUX = 0x1 P4yMUX = 0x2 P4yMUX = 0x3...

  • Page 89: Pd Port Group

    These five ports support the GPIO function. The GPIO function of the Pd2 port supports out- put only, therefore, the pull-up/down function cannot be used. Table 6.7.6.1 Control Registers for Pd Port Group (S1C17W14/W16) Register name Bit name...

  • Page 90: Common Registers Between Port Groups

    7–4 CLKDIV[3:0] R/WP 3–2 KRSTCFG[1:0] R/WP 1–0 CLKSRC[1:0] R/WP PINTFGRP 15–8 – 0x00 – – (P Port Interrupt Flag 7–5 – – Group Register) P4INT P3INT P2INT S1C17W16 only P1INT – P0INT Seiko Epson Corporation 6-18 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 91: Universal Port Multiplexer (Upmux)

    Notes: • ‘x’, which is used in the port names Pxy, register names, and bit names, refers to a port group (x = 0, 1, 2, 3) and ‘y’ refers to a port number (y = 0, 1, 2, ··· , 7). • The S1C17W14 UPMUX does not apply to P2[5:0]. Figure 7.1.1 shows the configuration of UPMUX.

  • Page 92: Control Registers

    These bits specify a peripheral circuit. (See Table 7.3.1.) Table 7.3.1 Peripheral I/O Function Selections PxUPMUXn.PxyPERISEL[2:0] bits (Peripheral circuit) None * SPIA UART T16B Reserved Reserved Reserved PxUPMUXn. PxUPMUXn.PxyPERICH[1:0] bits (Peripheral circuit channel) S1C17W14 PxyPPFNC[2:0] bits – 0x0, 0x1 0x0, 0x1 0x0, 0x1 – – – (Peripheral I/O –...

  • Page 93: Watchdog Timer (Wdt)

    = — — — — — — — — (Eq. 8.1) CLK_WDT Where Counter overflow cycle [second] CLK_WDT: WDT operating clock frequency [Hz] Example) = 4 seconds when CLK_WDT = 256 Hz Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 94: Clock Supply In Debug Mode

    If the clock source stops in SLEEP mode, WDT stops. To prevent generation of an unnecessary reset after clearing SLEEP mode, reset WDT before executing the slp instruction. WDT should also be stopped as required using the WDTCTL.WDTRUN[3:0] bits. Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 95: Control Registers

    WDTCNTRST Always read as 0. 3–0 WDTRUN[3:0] R/WP – Bits 15–5 Reserved Bit 4 WDTCNTRST This bit resets WDT. 1 (WP): Reset 0 (WP): Ignored 0 (R): Always 0 when being read Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)
  • Page 96 Always 0x0 is read if a value other than 0xa is written. Since a reset may be generated immediately after running depending on the counter value, WDT should also be reset concurrently when running WDT. Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 97: Real-Time Clock (Rtca)

    * Indicates the status when the pin is configured for RTCA. If the port is shared with the RTCA output function and other functions, the RTCA function must be assigned to the port. For more information, refer to the “I/O Ports” chapter. Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 98: Clock Settings

    · · · · · · · · · · · · · · · 0x3e 59.1 0x7e -1.9 0x3f 60.1 0x7f -1.0 Minimum resolution: 1 ppm, Correction rate range: -61.0 to 60.1 ppm Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 99: Operations

    3. Write 1 to the RTCINTF.ALARMIF bit to clear the alarm interrupt flag. 4. Write 1 to the RTCINTE.ALARMIE bit to enable alarm interrupts. When the real-time clock counter reaches the alarm time set in Step 2, an alarm interrupt occurs. Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 100: Real-Time Clock Counter Operations

    9.4.4 Stopwatch Count-up Pattern The stopwatch consists of 1/100-second and 1/10-second counters and these counters perform counting up in incre- ments of approximate 1/100 and 1/10 seconds with the count-up patterns shown in Figure 9.4.4.1. Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 101: Interrupts

    1 Hz counter value. • An alarm interrupt occurs after a lapse of 1/256 second from matching between the AM/PM (in 12H mode), hour, minute, and second counter value and the alarm setting value. Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 102: Control Registers

    Depending on these operation timings, the +1 second correction may be executed after the count-up operation resumes. For more information on the +1 second correction, refer to “Real-Time Clock Counter Operations.” Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 103: Rtc Second Alarm Register

    The RTCALM1.RTCSHA[2:0] bits and the RTCALM1.RTCSLA[3:0] bits set the 10-second digit and 1-second digit of the alarm time, respectively. A value within 0 to 59 seconds can be set in BCD code as shown in Table 9.6.1. Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 104: Rtc Hour/Minute Alarm Register

    SWRUN Bits 15–12 BCD10[3:0] Bits 11–8 BCD100[3:0] The 1/10-second and 1/100-second digits of the stopwatch counter can be read as a BCD code from the RTCSWCTL.BCD10[3:0] bits and the RTCSWCTL.BCD100[3:0] bits, respectively. Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 105: Rtc Second/1Hz Register

    1-second digit of the second counter, respectively. The setting/read values are a BCD code within the range from 0 to 59. Note: Be sure to avoid writing to the RTCSEC.RTCSH[2:0]/RTCSL[3:0] bits while the RTCCTL. RTCBSY bit = 1. Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 106: Rtc Hour/Minute Register

    1 to 12 in 12H mode or 0 to 23 in 24H mode. Note: Be sure to avoid writing to the RTCHUR.RTCHH[1:0]/RTCHL[3:0] bits while the RTCCTL. RTCBSY bit = 1. Bit 7 Reserved Seiko Epson Corporation 9-10 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 107: Rtc Month/Day Register

    The day of the week counter is a base-7 counter and the setting/read values are 0x0 to 0x6. Table 9.6.2 lists the correspondence between the count value and day of the week. Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL 9-11 (Rev. 1.2)

  • Page 108: Rtc Interrupt Flag Register

    The following shows the correspondence between the bit and interrupt: RTCINTF.RTCTRMIF bit: Theoretical regulation completion interrupt RTCINTF.SW1IF bit: Stopwatch 1 Hz interrupt RTCINTF.SW10IF bit: Stopwatch 10 Hz interrupt RTCINTF.SW100IF bit: Stopwatch 100 Hz interrupt Bits 11–9 Reserved Seiko Epson Corporation 9-12 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 109: Rtc Interrupt Enable Register

    The following shows the correspondence between the bit and interrupt: RTCINTE.RTCTRMIE bit: Theoretical regulation completion interrupt RTCINTE.SW1IE bit: Stopwatch 1 Hz interrupt RTCINTE.SW10IE bit: Stopwatch 10 Hz interrupt RTCINTE.SW100IE bit: Stopwatch 100 Hz interrupt Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL 9-13 (Rev. 1.2)
  • Page 110 RTCINTE.1DAYIE bit: 1-day interrupt RTCINTE.1HURIE bit: 1-hour interrupt RTCINTE.1MINIE bit: 1-minute interrupt RTCINTE.1SECIE bit: 1-second interrupt RTCINTE.1_2SECIE bit: 1/2-second interrupt RTCINTE.1_4SECIE bit: 1/4-second interrupt RTCINTE.1_8SECIE bit: 1/8-second interrupt RTCINTE.1_32SECIE bit: 1/32-second interrupt Seiko Epson Corporation 9-14 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 111: Supply Voltage Detector (Svd)

    Clock generator CLKDIV[2:0] DBRUN SVDC[4:0] EXSVD Voltage VDSEL comparator SVDDT circuit Detection SVDSC[1:0] SVDIF result counter SVDIE SVDRE[3:0] Interrupt/reset To system reset circuit control circuit To interrupt controller Figure 10.1.1 SVD Configuration Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL 10-1 (Rev. 1.2)

  • Page 112: Input Pin And External Connection

    SLEEP mode and SVD stops with the register settings maintained at those before entering SLEEP mode. After the CPU returns to normal mode, CLK_SVD is supplied and the SVD operation resumes. Seiko Epson Corporation 10-2 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 113: Clock Supply In Debug Mode

    SVDCTL.MODEN bit = 1, wait for at least SVD circuit response time before reading the SVDINTF.SVDDT bit (refer to “Supply Voltage Detector Characteristics, SVD circuit response time t ” in the “Electrical Char- acteristics” chapter). Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL 10-3 (Rev. 1.2)

  • Page 114: Svd Operations

    SVDIF bit). An interrupt request is sent to the interrupt controller only when the SVDINTF.SVDIF bit is set while the interrupt is enabled by the SVDINTE.SVDIE bit. For more information on interrupt control, refer to the “Interrupt Controller” chapter. Seiko Epson Corporation 10-4 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 115: Svd Reset

    Bit 7 Reserved Bits 6–4 CLKDIV[2:0] These bits select the division ratio of the SVD operating clock. Bits 3–2 Reserved Bits 1–0 CLKSRC[1:0] These bits select the clock source of SVD. Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL 10-5 (Rev. 1.2)

  • Page 116: Svd Control Register

    SVD detection voltage V 0x1e High 0x1d ↑ 0x1c 0x02 ↓ 0x01 0x00, 0x1f Use prohibited For more information, refer to “Supply Voltage Detector Characteristics, SVD detection voltage ” in the “Electrical Characteristics” chapter. Seiko Epson Corporation 10-6 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 117: Svd Status And Interrupt Flag Register

    This bit indicates the low power supply voltage detection interrupt cause occurrence status. 1 (R): Cause of interrupt occurred 0 (R): No cause of interrupt occurred 1 (W): Clear flag 0 (W): Ineffective Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL 10-7 (Rev. 1.2)

  • Page 118: Svd Interrupt Enable Register

    • To prevent generating unnecessary interrupts, the corresponding interrupt flag should be cleared before enabling interrupts. Seiko Epson Corporation 10-8 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 119: 16-Bit Timers (T16)

    • A clock source and clock division ratio for generating the count clock are selectable. • Repeat mode or one-shot mode is selectable. • Can generate counter underflow interrupts. Figure 11.1.1 shows the configuration of a T16 channel. Table 11.1.1 T16 Channel Configuration of S1C17W14/W16 Item S1C17W14 S1C17W16 Number of channels 3 channels (Ch.0–Ch.2)

  • Page 120: Clock Settings

    (Set reload data (counter preset data)) 5. Set the following bits when using the interrupt: - Write 1 to the T16_nINTF.UFIF bit. (Clear interrupt flag) - Set the T16_nINTE.UFIE bit to 1. (Enable underflow interrupt) Seiko Epson Corporation 11-2 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 121: Counter Underflow

    At the same time the counter stops, the T16_ nCTL.PRUN bit is cleared automatically. Select this mode to stop the counter after an interrupt has occurred once, such as for checking a specific lapse of time. Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL 11-3 (Rev. 1.2)

  • Page 122: Counter Value Read

    Bits 7–4 CLKDIV[3:0] These bits select the division ratio of the T16 Ch.n operating clock (counter clock). Bits 3–2 Reserved Bits 1–0 CLKSRC[1:0] These bits select the clock source of T16 Ch.n. Seiko Epson Corporation 11-4 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 123: T16 Ch.n Mode Register

    PRESET MODEN Bits 15–9 Reserved Bit 8 PRUN This bit starts/stops the timer. 1 (W): Start timer 0 (W): Stop timer 1 (R): Timer is running 0 (R): Timer is idle Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL 11-5 (Rev. 1.2)

  • Page 124: T16 Ch.n Reload Data Register

    This bit indicates the T16 Ch.n underflow interrupt cause occurrence status. 1 (R): Cause of interrupt occurred 0 (R): No cause of interrupt occurred 1 (W): Clear flag 0 (W): Ineffective Seiko Epson Corporation 11-6 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 125: T16 Ch.n Interrupt Enable Register

    This bit enables T16 Ch.n underflow interrupts. 1 (R/W): Enable interrupts 0 (R/W): Disable interrupts Note: To prevent generating unnecessary interrupts, the corresponding interrupt flag should be cleared before enabling interrupts. Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL 11-7 (Rev. 1.2)

  • Page 126: Uart (Uart)

    • Input pin can be pulled up with an internal resistor. • The output pin is configurable as an open-drain output. Figure 12.1.1 shows the UART configuration. Table 12.1.1 UART Channel Configuration of S1C17W14/W16 Item S1C17W14 S1C17W16 Number of channels 2 channels (Ch.0 and Ch.1)

  • Page 127: Input/Output Pins And External Connections

    When using the UART during SLEEP mode, the UART operating clock CLK_UARTn must be configured so that it will keep supplying by writing 0 to the CLGOSC.xxxxSLPC bit for the CLK_UARTn clock source. Seiko Epson Corporation 12-2 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 128: Clock Supply In Debug Mode

    (UAnMOD.STPB bit = 1). Parity function The parity function is configured using the UAnMOD.PREN and UAnMOD.PRMD bits. Table 12.4.1 Parity Function Setting UAnMOD.PREN bit UAnMOD.PRMD bit Parity function Odd parity Even parity Non parity Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL 12-3 (Rev. 1.2)

  • Page 129: Operations

    2. Write transmit data to the UAnTXD register. 3. Wait for a UART interrupt when using the interrupt. 4. Repeat Steps 1 to 3 (or 1 and 2) until the end of transmit data. Seiko Epson Corporation 12-4 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 130: Data Reception

    2. Check to see if the UAnINTF.RB1FIF bit is set to 1 (receive buffer one byte full). 3. Read the received data from the UAnRXD register. 4. Repeat Steps 1 to 3 (or 2 and 3) until the end of data reception. Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL 12-5 (Rev. 1.2)

  • Page 131: Irda Interface

    Set the UAnMOD.IRMD bit to 1 to use the IrDA interface. Data transfer control is identical to that for normal interface even if the IrDA interface function is enabled. Seiko Epson Corporation 12-6 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 132: Receive Errors

    Note, however, that the set timing depends on the buffer status at that point. • When the receive data buffer is empty The interrupt flag will be set when the data that encountered an error is transferred to the re- ceive data buffer. Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL 12-7 (Rev. 1.2)

  • Page 133: Parity Error

    12.8 Control Registers UART Ch.n Clock Control Register Register name Bit name Initial Reset Remarks UAnCLK 15–9 – 0x00 – – DBRUN 7–6 – – 5–4 CLKDIV[1:0] 3–2 – – 1–0 CLKSRC[1:0] Seiko Epson Corporation 12-8 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 134: Uart Ch.n Mode Register

    1 (R/W): Enable output inverting function 0 (R/W): Disable output inverting function Bit 7 Reserved Bit 6 PUEN This bit enables pull-up of the USINn pin. 1 (R/W): Enable pull-up 0 (R/W): Disable pull-up Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL 12-9 (Rev. 1.2)

  • Page 135: Uart Ch.n Baud-Rate Register

    Note: The UAnBR register settings can be altered only when the UAnCTL.MODEN bit = 0. UART Ch.n Control Register Register name Bit name Initial Reset Remarks UAnCTL 15–8 – 0x00 – – 7–2 – 0x00 – SFTRST MODEN Bits 15–2 Reserved Seiko Epson Corporation 12-10 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 136: Uart Ch.n Transmit Data Register

    PEIF H0/S0 OEIF H0/S0 Cleared by writing 1. RB2FIF H0/S0 Cleared by reading the UAnRXD reg- ister. RB1FIF H0/S0 TBEIF H0/S0 Cleared by writing to the UAnTXD register. Bits 15–10 Reserved Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL 12-11 (Rev. 1.2)
  • Page 137 Bit 5 FEIE Bit 4 PEIE Bit 3 OEIE Bit 2 RB2FIE Bit 1 RB1FIE Bit 0 TBEIE These bits enable UART interrupts. 1 (R/W): Enable interrupts 0 (R/W): Disable interrupts Seiko Epson Corporation 12-12 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)
  • Page 138 UAnINTE.PEIE bit: Parity error interrupt UAnINTE.OEIE bit: Overrun error interrupt UAnINTE.RB2FIE bit: Receive buffer two bytes full interrupt UAnINTE.RB1FIE bit: Receive buffer one byte full interrupt UAnINTE.TBEIE bit: Transmit buffer empty interrupt Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL 12-13 (Rev. 1.2)

  • Page 139: Synchronous Serial Interface (Spia)

    • Slave mode is capable of being operated in SLEEP mode allowing wake-up by an SPIA interrupt. • Input pins can be pulled up/down with an internal resistor. Figure 13.1.1 shows the SPIA configuration. Table 13.1.1 SPIA Channel Configuration of S1C17W14/W16 Item S1C17W14...

  • Page 140: Input/Output Pins And External Connections

    SDIn #SPISS0 SPICLKn #SPISS1 #SPISS #SPISS2 External SPI master device External SPI slave devices SPICLK SPICLK #SPISS SPICLK Figure 13.2.2.2 Connections between SPIA in Slave Mode and External SPI Master Device Seiko Epson Corporation 13-2 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 141: Pin Functions In Master Mode And Slave Mode

    16-bit timer channel and converts it to the SPICLKn. The 16-bit timer must be run with an appro- priate reload data set. The SPICLKn frequency (baud rate) and the 16-bit timer reload data are calculated by the equations shown below. Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL 13-3 (Rev. 1.2)

  • Page 142: Clock Supply In Debug Mode

    SDIn SDOn (Master mode) SDOn (Slave mode) SDOn (Slave mode) Writing data to the SPInTXD register Figure 13.3.3.1 SPI Clock Phase and Polarity (SPInMOD.LSBFST bit = 0, SPInMOD.CHLN[3:0] bits = 0x7) Seiko Epson Corporation 13-4 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 143: Data Format

    1. Assert the slave select signal by controlling the general-purpose output port (if necessary). 2. Check to see if the SPInINTF.TBEIF bit is set to 1 (transmit buffer empty). 3. Write transmit data to the SPInTXD register. Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL 13-5 (Rev. 1.2)
  • Page 144 SPInTXD register Transmit data remained? Wait for an interrupt request (SPInINTF.TBEIF = 1) Negate the slave select signal output from a general-purpose port Figure 13.5.2.2 Data Transmission Flowchart in Master Mode Seiko Epson Corporation 13-6 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 145: Data Reception In Master Mode

    Software operations SPInRXD → Data (R) Data (W) → SPInTXD SPInRXD → Data (R) 1 (W) → SPInINTF.TENDIF Figure 13.5.3.1 Example of Data Receiving Operations in Master Mode (SPInMOD.CHLN[3:0] bits = 0x7) Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL 13-7 (Rev. 1.2)

  • Page 146: Terminating Data Transfer In Master Mode

    SPInTXD register data written is completed. If no transmit data is written during this period, the data bits input from the SDIn pin are shifted and output from the SDOn pin without being modified. Seiko Epson Corporation 13-8 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)
  • Page 147 Data (W) → SPInTXD Data (W) → SPInTXD Software operations SPInRXD → Data (R) SPInRXD → Data (R) Figure 13.5.5.1 Example of Data Transfer Operations in Slave Mode (SPInMOD.CHLN[3:0] bits = 0x7) Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL 13-9 (Rev. 1.2)

  • Page 148: Terminating Data Transfer In Slave Mode

    “Interrupt Controller” chapter. The SPInINTF register also contains the BSY bit that indicates the SPIA operating status. Figure 13.6.1 shows the SPInINTF.BSY and SPInINTF.TENDIF bit set timings. Seiko Epson Corporation 13-10 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 149: Control Registers

    Remarks SPInMOD 15–12 – – – 11–8 CHLN[3:0] 7–6 – – PUEN NOCLKDIV LSBFST CPHA CPOL Bits 15–12 Reserved Bits 11–8 CHLN[3:0] These bits set the bit length of transfer data. Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL 13-11 (Rev. 1.2)

  • Page 150: Spia Ch.n Control Register

    Note: The SPInMOD register settings can be altered only when the SPInCTL.MODEN bit = 0. SPIA Ch.n Control Register Register name Bit name Initial Reset Remarks SPInCTL 15–8 – 0x00 – – 7–2 – 0x00 – SFTRST MODEN Bits 15–2 Reserved Seiko Epson Corporation 13-12 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 151: Spia Ch.n Transmit Data Register

    0x00 – – 6–4 – – OEIF H0/S0 Cleared by writing 1. TENDIF H0/S0 RBFIF H0/S0 Cleared by reading the SPInRXD register. TBEIF H0/S0 Cleared by writing to the SPInTXD register. Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL 13-13 (Rev. 1.2)

  • Page 152: Spia Ch.n Interrupt Enable Register

    The following shows the correspondence between the bit and interrupt: SPInINTE.OEIE bit: Overrun error interrupt SPInINTE.TENDIE bit: End-of-transmission interrupt SPInINTE.RBFIE bit: Receive buffer full interrupt SPInINTE.TBEIE bit: Transmit buffer empty interrupt Seiko Epson Corporation 13-14 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 153: C (I2C)

    • The input filter for the SDA and SCL inputs does not comply with the standard for removing noise spikes less than 50 ns. Figure 14.1.1 shows the I2C configuration. Table 14.1.1 I2C Channel Configuration of S1C17W14/W16 Item S1C17W14 S1C17W16 Number of channels 1 channel (Ch.0)

  • Page 154: Input/Output Pins And External Connections

    • The internal pull-up resistors for the I/O ports cannot be used for pulling up SDA and SCL. • When the I2C is set into master mode, no other master device can be connected to the I bus. Seiko Epson Corporation 14-2 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 155: Clock Settings

    14.3.3.1). Note: The I C bus transfer rate is limited to 100 kbit/s in standard mode or 400 kbit/s in fast mode. Do not set a transfer rate exceeding the limit. Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL 14-3 (Rev. 1.2)

  • Page 156: Operations

    - Set the I2CnCTL.MST bit to 0. (Set slave mode) - Set the I2CnCTL.SFTRST bit to 1. (Execute software reset) - Set the I2CnCTL.MODEN bit to 1. (Enable I2C Ch.n operations) Seiko Epson Corporation 14-4 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 157: Data Transmission In Master Mode

    I2CnINTF.NACKIF bit = 1 (NACK received), the I2C Ch.n generates a repeated START condition. When the repeated START condition has been generated, the I2CnINTF.STARTIF and I2CnINTF.TBEIF bits are both set to 1 same as when a START condition has been generated. Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL 14-5 (Rev. 1.2)
  • Page 158 Last data sent? Retry? Write 1 to the I2CnCTL.TXSTOP bit Write data to the I2CnTXD register Wait for an interrupt request (I2CnINTF.STOPIF = 1) Figure 14.4.2.2 Master Mode Data Transmission Flowchart Seiko Epson Corporation 14-6 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 159: Data Reception In Master Mode

    This reading triggers the I2C Ch.n to start subsequent data reception. Generating a STOP or repeated START condition It is the same as the data transmission in master mode. Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL 14-7 (Rev. 1.2)
  • Page 160 Read receive data from the I2CnRXD register Write 1 to the I2CnCTL.TXSTOP bit Write 1 to the I2CnCTL.TXSTOP bit Wait for an interrupt request (I2CnINTF.STOPIF = 1) Figure 14.4.3.2 Master Mode Data Reception Flowchart Seiko Epson Corporation 14-8 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 161: 10-Bit Addressing In Master Mode

    Clear the I2CnINTF.STARTIF bit by writing 1 after the interrupt has occurred. 9. Write the first address to the I2CnTXD.TXD[7:1] bits and 1 that represents READ as the data transfer direc- tion to the I2CnTXD.TXD0 bit. 10. Perform data reception. Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL 14-9 (Rev. 1.2)

  • Page 162: Data Transmission In Slave Mode

    Go to Step 6 when a STOP condition interrupt has occurred. ii. Go to Step 2 when a START condition interrupt has occurred. 6. Clear the I2CnINTF.STOPIF bit and then terminate data sending operations. Seiko Epson Corporation 14-10 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)
  • Page 163 A: ACK, A: NACK, Saddr/R: Slave address + R(1), Saddr/W: Slave address + W(0), STARTIF = 1 Data n: 8-bit data Figure 14.4.5.1 Example of Data Sending Operations in Slave Mode Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL 14-11 (Rev. 1.2)

  • Page 164: Data Reception In Slave Mode

    I2C Ch.n sends an ACK and pulls down SCL to low. The received data in the shift register is transferred to the receive data buffer and the I2CnINTF.RBFIF and I2CnINTF.BYTEENDIF bits are both set to 1. Af- ter that, the received data can be read out from the I2CnRXD register. Seiko Epson Corporation 14-12 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)
  • Page 165 Wait for an interrupt request (I2CnINTF.RBFIF = 1) Last data received next? Write 1 to the I2CnCTL.TXNACK bit Read receive data from the I2CnRXD register Last data received? Figure 14.4.6.2 Slave Mode Data Reception Flowchart Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL 14-13 (Rev. 1.2)

  • Page 166: Slave Operations In 10-Bit Address Mode

    If SDA does not change from low when the I2C Ch.n outputs the ninth clock, it is regarded as an automatic bus clearing failure. In this case, the I2C Ch.n clears the I2CnCTL.TXSTART bit to 0 and sets both the I2CnINTF.ERRIF and I2CnINTF.STARTIF bits to 1. Seiko Epson Corporation 14-14 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 167: Error Detection

    4 <Master mode only> When 1 is written to the I2CnCTL.TX- I2CnINTF.ERRIF = 1 START bit while the I2CnINTF.BSY bit = 0 (Refer to “Automatic Automatic bus clearing I2CnCTL.TXSTART = 0 Bus Clearing Operation.”) failure I2CnINTF.STARTIF = 1 Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL 14-15 (Rev. 1.2)

  • Page 168: Interrupts

    Master mode BRT + 3 CLK_I2Cn TXSTART = 1 TXSTART = 0 STARTIF = 1 Slave mode Address matching the I2CnOADR register BSY = 1 TR = 0/1 STARTIF = 1 Seiko Epson Corporation 14-16 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 169: Control Registers

    (Note) The oscillation circuits/external input that are not supported in this IC cannot be selected as the clock source. Note: The I2CnCLK register settings can be altered only when the I2CnCTL.MODEN bit = 0. Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL 14-17 (Rev. 1.2)

  • Page 170: I2C Ch.n Mode Register

    The I2CnOADR.OADR[9:0] bits are effective in 10-bit address mode (I2CnMOD.OADR10 bit = 1), or the I2CnOADR.OADR[6:0] bits are effective in 7-bit address mode (I2CnMOD.OADR10 bit = 0). Note: The I2CnOADR register settings can be altered only when the I2CnCTL.MODEN bit = 0. Seiko Epson Corporation 14-18 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 171: I2C Ch.n Control Register

    Bit 0 MODEN This bit enables the I2C operations. 1 (R/W): Enable I2C operations (The operating clock is supplied.) 0 (R/W): Disable I2C operations (The operating clock is stopped.) Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL 14-19 (Rev. 1.2)

  • Page 172: I2C Ch.n Transmit Data Register

    0 (R): SDA = High level Bit 11 SCLLOW This bit indicates that SCL is set to low level. 1 (R): SCL = Low level 0 (R): SCL = High level Seiko Epson Corporation 14-20 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 173: I2C Ch.n Interrupt Enable Register

    Transmit buffer empty interrupt I2C Ch.n Interrupt Enable Register Register name Bit name Initial Reset Remarks I2CnINTE 15–8 – 0x00 – – BYTEENDIE GCIE NACKIE STOPIE STARTIE ERRIE RBFIE TBEIE Bits 15–8 Reserved Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL 14-21 (Rev. 1.2)
  • Page 174 I2CnINTE.NACKIE bit: NACK reception interrupt I2CnINTE.STOPIE bit: STOP condition interrupt I2CnINTE.STARTIE bit: START condition interrupt I2CnINTE.ERRIE bit: Error detection interrupt I2CnINTE.RBFIE bit: Receive buffer full interrupt I2CnINTE.TBEIE bit: Transmit buffer empty interrupt Seiko Epson Corporation 14-22 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 175: 16-Bit Pwm Timers (T16B)

    - The capture circuit captures counter values using external/software trigger signals and generates interrupts. (Can be used to measure external event periods/cycles.) Figure 15.1.1 shows the T16B configuration. Table 15.1.1 T16B Channel Configuration of S1C17W14/W16 Item S1C17W14 S1C17W16 Number of channels 2 channels (Ch.0 and Ch.1)

  • Page 176: Input/Output Pins

    If the port is shared with the T16B pin and other functions, the T16B input/output function must be assigned to the port before activating T16B. For more information, refer to the “I/O Ports” chapter. Seiko Epson Corporation 15-2 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 177: Clock Settings

    Figure 15.3.4.1 Count Timing (During Count Up Operation) Note: When running the counter using the event counter clock, two dummy clocks must be input be- fore the first counting up/down can be performed. Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL 15-3 (Rev. 1.2)

  • Page 178: Operations

    - T16BnCTL.CNTMD[1:0] bits (Select count up/down operation) - T16BnCTL.ONEST bit (Select one-shot/repeat operation) - Set the T16BnCTL.PRESET bit to 1. (Reset counter) - Set the T16BnCTL.RUN bit to 1. (Start counting) Seiko Epson Corporation 15-4 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 179: Counter Block Operations

    MAX value. If the MAX value is altered to a value smaller than the current counter value, the counter is cleared to 0x0000 and continues counting up to the new MAX value. Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL 15-5 (Rev. 1.2)
  • Page 180 MODEN = 1 PRESET = 1 RUN = 1 Software operation Data (W) → MC[15:0] RUN = 1 RUN = 0 Hardware operation 0xffff Count cycle MAX value Counter Time 0x0000 Seiko Epson Corporation 15-6 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)
  • Page 181 Data (W) → MC[15:0] RUN = 1 RUN = 1 0xffff MAX value Counter Time 0x0000 RUN = 0 Figure 15.4.2.3 Operations in Repeat Up/Down Count and One-shot Up/Down Count Modes Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL 15-7 (Rev. 1.2)

  • Page 182: Comparator/Capture Block Operations

    MAX value (T16BnMC register) Counter Comparison value (T16BnCCRm register) Compare period Time 0x0000 CNTZEROIF = 1 CNTZEROIF = 1 CNTZEROIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 Seiko Epson Corporation 15-8 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)
  • Page 183 (T16BnMC register) Compare period Compare buffer Counter value Time 0x0000 CNTMAXIF = 1 CNTMAXIF = 1 CNTMAXIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL 15-9 (Rev. 1.2)
  • Page 184 (T16BnMC register) Compare period Compare buffer Counter value Time 0x0000 CNTMAXIF = 1 CNTMAXIF = 1 CNTMAXIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 Seiko Epson Corporation 15-10 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)
  • Page 185 (T16BnMC register) Counter Compare buffer value Compare period Time 0x0000 CNTZEROIF = 1 CNTZEROIF = 1 CNTZEROIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL 15-11 (Rev. 1.2)
  • Page 186 (T16BnMC register) Counter Compare buffer value Compare period Time 0x0000 CNTZEROIF = 1 CNTZEROIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 Seiko Epson Corporation 15-12 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)
  • Page 187 Compare period during counting down Time 0x0000 CNTMAXIF = 1 CNTZEROIF = 1 CNTMAXIF = 1 CNTZEROIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL 15-13 (Rev. 1.2)
  • Page 188 If the captured data stored in the T16BnCCRm register is overwritten by the next trigger when the T16BnINTF. CMPCAPmIF bit is still set, an overwrite error occurs (the T16BnINTF.CAPOWmIF bit is set). Seiko Epson Corporation 15-14 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)
  • Page 189 Capture trigger signal T16BnCCRm.CC[15:0] Capturing operation (2) Asynchronous capture mode (When T16BnCCCTLm.CAPTRG[1:0] bits = 0x3) Count clock T16BnTC.TC[15:0] Capture trigger signal T16BnCCRm.CC[15:0] Capturing operation Figure 15.4.3.4 Synchronous Capture Mode/Asynchronous Capture Mode Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL 15-15 (Rev. 1.2)

  • Page 190: Tout Output Control

    The TOUT signal polarity (active level) can be set using the T16BnCCCTLm.TOUTINV bit. It is set to active high by setting the T16BnCCCTLm.TOUTINV bit to 0 and active low by setting to 1. Figures 15.4.4.2 and 15.4.4.3 show the TOUT output waveforms. Seiko Epson Corporation 15-16 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)
  • Page 191 Software control mode (0x0) Set mode (0x1) Toggle/reset mode (0x2) Set/reset mode (0x3) Toggle mode(0x4) Reset mode (0x5) Toggle/set mode (0x6) Reset/set mode (0x7) ∗ ( ) indicates the T16BnCCCTLm.TOUTMD[2:0] bit-setting value. Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL 15-17 (Rev. 1.2)
  • Page 192 Set/reset mode (0x3) Toggle mode(0x4) Reset mode (0x5) Toggle/set mode (0x6) Reset/set mode (0x7) ∗ ( ) indicates the T16BnCCCTLm.TOUTMD[2:0] bit-setting value. Figure 15.4.4.2 TOUT Output Waveform (T16BnCCCTLm.TOUTMT bit = 0) Seiko Epson Corporation 15-18 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)
  • Page 193 Set/reset mode (0x3) TOUTn0 TOUTn1 Toggle mode(0x4) TOUTn0 TOUTn1 Reset mode (0x5) TOUTn0 TOUTn1 Toggle/set mode (0x6) TOUTn0 TOUTn1 Reset/set mode (0x7) TOUTn0 TOUTn1 ∗ ( ) indicates the T16BnCCCTLm.TOUTMD[2:0] bit-setting value. Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL 15-19 (Rev. 1.2)
  • Page 194 Set/reset mode (0x3) TOUTn0 TOUTn1 Toggle mode(0x4) TOUTn0 TOUTn1 Reset mode (0x5) TOUTn0 TOUTn1 Toggle/set mode (0x6) TOUTn0 TOUTn1 Reset/set mode (0x7) TOUTn0 TOUTn1 ∗ ( ) indicates the T16BnCCCTLm.TOUTMD[2:0] bit-setting value. Seiko Epson Corporation 15-20 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)
  • Page 195 Toggle/set mode (0x6) TOUTn0 TOUTn1 Reset/set mode (0x7) TOUTn0 TOUTn1 ∗ ( ) indicates the T16BnCCCTLm.TOUTMD[2:0] bit-setting value. Figure 15.4.4.3 TOUT Output Waveform (T16BnCCCTL0.TOUTMT bit = 1, T16BnCCCTL1.TOUTMT bit = 0) Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL 15-21 (Rev. 1.2)

  • Page 196: Interrupt

    Bits 7–4 CLKDIV[3:0] These bits select the division ratio of the T16B Ch.n operating clock (counter clock). Bit 3 Reserved Bits 2–0 CLKSRC[2:0] These bits select the clock source of T16B Ch.n. Seiko Epson Corporation 15-22 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 197: T16B Ch.n Counter Control Register

    T16BnCTL.ONEST bit setting (see Table 15.6.2). Bit 3 ONEST This bit selects the counter repeat/one-shot mode. The count mode is configured with this selection and the T16BnCTL.CNTMD[1:0] bit settings (see Table 15.6.2). Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL 15-23 (Rev. 1.2)

  • Page 198: T16B Ch.n Max Counter Data Register

    T16BnCTL.MODEN bit to 1 until the T16BnCS.BSY bit is set to 0 from 1. • Do not set the T16BnMC.MC[15:0] bits to 0x0000. T16B Ch.n Timer Counter Data Register Register name Bit name Initial Reset Remarks T16BnTC 15–0 TC[15:0] 0x0000 – Seiko Epson Corporation 15-24 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 199: T16B Ch.n Counter Status Register

    This bit indicates the currently set count direction. 1 (R): Count up 0 (R): Count down Bit 0 This bit indicates the counter operating status. 1 (R): Running 0 (R): Idle Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL 15-25 (Rev. 1.2)

  • Page 200: T16B Ch.n Interrupt Flag Register

    Note: The configuration of the T16BnINTF.CAPOWmIF and T16BnINTF.CMPCAPmIF bits depends on the model. The bits corresponding to the comparator/capture circuits that do not exist are read-only bits and are always fixed at 0. Seiko Epson Corporation 15-26 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 201: T16B Ch.n Interrupt Enable Register

    The bits corresponding to the comparator/capture circuits that do not exist are read-only bits and are always fixed at 0. • To prevent generating unnecessary interrupts, the corresponding interrupt flag should be cleared before enabling interrupts. Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL 15-27 (Rev. 1.2)

  • Page 202: T16B Ch.n Comparator/Capture M Control Register

    These bits select the trigger edge(s) of the trigger signal at which the counter value is captured in the T16BnCCRm register in capture mode (see Table 15.6.4). The T16BnCCCTLm.CAPTRG[1:0] bits are control bits for capture mode and are ineffective in comparator mode. Seiko Epson Corporation 15-28 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)
  • Page 203 The signal becomes inactive by the MATCH signal. All count modes TOUTnm The signal becomes inactive by the MATCHm or MATCHm+1 signal. TOUTnm+1 The signal becomes inactive by the MATCHm+1 or MATCHm signal. Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL 15-29 (Rev. 1.2)

  • Page 204: T16B Ch.n Compare/Capture M Data Register

    In capture mode, this register is configured as the capture register and the counter value captured by the capture trigger signal is loaded. Seiko Epson Corporation 15-30 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 205: Sound Generator (Snda)

    Clock generator DBRUN MODEN SBSY Sound register MOSEL[1:0] Sound generation STIM[3:0] circuit BZOUT SINV Output control circuit SSTP #BZOUT Interrupt controller Interrupt control circuit EMIE EMIF EDIE EDIF Figure 16.1.1 SNDA Configuration Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL 16-1 (Rev. 1.2)

  • Page 206: Output Pins And External Connections

    Piezoelectric buzzer #BZOUT S1C17 SNDA Figure 16.2.2.1 Connection between SNDA and Piezoelectric Buzzer (Direct Drive) Piezoelectric buzzer BZOUT S1C17 SNDA Figure 16.2.2.2 Connection between SNDA and Piezoelectric Buzzer (Single Pin Drive) Seiko Epson Corporation 16-2 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 207: Clock Settings

    IC. The buzzer output duration can also be controlled via software. An output start/stop procedure and the SNDA operations are shown below. Normal buzzer output start/stop procedure 1. Set the SNDSEL.MOSEL[1:0] bits to 0x0. (Set normal buzzer mode) Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL 16-3 (Rev. 1.2)
  • Page 208 Buzzer signal frequency [Hz] BZOUT DUTY: Buzzer signal duty ratio [%] However, the following settings are prohibited: • Settings as SNDDAT.SFRQ[7:0] bits ≤ SNDDAT.SLEN[5:0] bits • Settings as SNDDAT.SFRQ[7:0] bits = 0x00 Seiko Epson Corporation 16-4 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)
  • Page 209 – 71.9 35.9 0x15 – – – – 68.8 34.4 0x14 – – – – 65.6 32.8 0x13 – – – – 62.5 31.3 0x12 – – – – 59.4 29.7 Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL 16-5 (Rev. 1.2)

  • Page 210: Buzzer Output In One-Shot Buzzer Mode

    At the same time, the SNDINTF.EDIF bit (sound output completion interrupt flag) is set to 1 and the SND- INTF.SBSY bit is cleared to 0. Figure 16.4.3.1 shows a buzzer output timing chart in one-shot buzzer mode. Seiko Epson Corporation 16-6 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 211: Output In Melody Mode

    At the same time, the SNDINTF.EDIF bit (sound output completion interrupt flag) is set to 1 and the SNDINTF.SBSY bit is cleared to 0. Figure 16.4.4.1 shows a melody mode operation timing chart. Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL 16-7 (Rev. 1.2)
  • Page 212 = 32,768 Hz) CLK_SNDA SNDDAT.SFRQ[7:0] bits Scale Frequency [Hz] 0xf8 131.60 0xea 139.44 0xdd 147.60 0xd1 156.04 0xc5 165.49 0xba 175.23 0xaf 186.18 0xa5 197.40 0x9c 208.71 0x93 221.41 0x8b 234.06 Seiko Epson Corporation 16-8 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 213: Interrupts

    This bit sets whether the SNDA operating clock is supplied in DEBUG mode or not. 1 (R/W): Clock supplied in DEBUG mode 0 (R/W): No clock supplied in DEBUG mode Bit 7 Reserved Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL 16-9 (Rev. 1.2)

  • Page 214: Snda Select Register

    187.5 43.6 171.9 156.3 53.3 140.6 125.0 68.6 109.4 93.8 78.1 62.5 46.9 31.3 15.6 Note: Be sure to avoid altering these bits when SNDINTF.SBSY bit = 1. Bits 7–3 Reserved Seiko Epson Corporation 16-10 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 215: Snda Control Register

    This bit specifies a tie or slur (continuous play with the previous note) in melody mode. 1 (R/W): Enable tie/slur 0 (R/W): Disable tie/slur This bit is ignored in normal buzzer mode/one-shot buzzer mode. Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL 16-11 (Rev. 1.2)

  • Page 216: Snda Interrupt Flag Register

    No cause of interrupt occurred 1 (W): Clear flag 0 (W): Ineffective The following shows the correspondence between the bit and interrupt: SNDINTF.EMIF bit: Sound buffer empty interrupt SNDINTF.EDIF bit: Sound output completion interrupt Seiko Epson Corporation 16-12 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 217: Snda Interrupt Enable Register

    These bits enable SNDA interrupts. 1 (R/W): Enable interrupts 0 (R/W): Disable interrupts The following shows the correspondence between the bit and interrupt: SNDINTE.EMIE bit: Sound buffer empty interrupt SNDINTE.EDIE bit: Sound output completion interrupt Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL 16-13 (Rev. 1.2)

  • Page 218: Ir Remote Controller (Remc2)

    • Automatic data setting function for continuous data transmission. • Output signal inverting function supporting various formats. • EL lamp drive waveform can be generated for an application example. Figure 17.1.1 shows the REMC2 configuration. Table 17.1.1 REMC2 Channel Configuration of S1C17W14/W16 Item S1C17W14 S1C17W16...

  • Page 219: External Connections

    1. Write 1 to the REMDBCTL.REMCRST bit. (Reset REMC2) 2. Configure the REMCLK.CLKSRC[1:0] and REMCLK.CLKDIV[3:0] bits. (Configure operating clock) 3. Assign the REMC2 output function to the port. (Refer to the “I/O Ports” chapter.) Seiko Epson Corporation 17-2 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 220: Data Transmission Procedures

    The REMC2 outputs the logical AND between the carrier signal output from the carrier generator and the data sig- nal output from the data signal generator. Figure 17.4.3.1 shows an example of the output waveform. Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL 17-3 (Rev. 1.2)
  • Page 221 The data signal is generated by comparing the values of the 16-bit counter for data signal generation (REM- DBCNT.DBCNT[15:0] bits) that runs with CLK_REMC2 and the setting values of the REMAPLEN. APLEN[15:0] and REMDBLEN.DBLEN[15:0] bits. Figure 17.4.3.3 shows an example of the data signal gen- erated. Seiko Epson Corporation 17-4 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 222: Continuous Data Transmission And Compare Buffers

    (REMDBCTL.TRMD bit = 1), the counter stops automatically when the counter value is matched with the REMDBLEN.DBLEN[15:0] bit-setting value. 17.4.4 Continuous Data Transmission and Compare Buffers Figure 17.4.4.1 shows an operation example of continuous data transmission with the compare buffer enabled. Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL 17-5 (Rev. 1.2)

  • Page 223: Interrupts

    For more information on interrupt control, refer to the “Interrupt Controller” chapter. Seiko Epson Corporation 17-6 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 224: Application Example: Driving El Lamp

    1 (R/W): Clock supplied in DEBUG mode 0 (R/W): No clock supplied in DEBUG mode Bits 7–4 CLKDIV[3:0] These bits select the division ratio of the REMC2 operating clock. Bits 3–2 Reserved Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL 17-7 (Rev. 1.2)

  • Page 225: Remc2 Data Bit Counter Control Register

    This bit starts/stops counting by the internal counters (16-bit counter for data signal generation and 8-bit counter for carrier generation). 1 (W): Start counting 0 (W): Stop counting 1 (R): Counting 0 (R): Idle Seiko Epson Corporation 17-8 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 226: Remc2 Data Bit Counter Register

    0x0000 H0/S0 Cleared by writing 1 to the REMDBCTL.REMCRST bit. Bits 15–0 DBCNT[15:0] The current value of the 16-bit counter for data signal generation can be read out through these bits. Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL 17-9 (Rev. 1.2)

  • Page 227: Remc2 Data Bit Active Pulse Length Register

    This bit indicates whether the value written to the REMAPLEN.APLEN[15:0] bits is transferred to the REMAPLEN buffer or not. (See Figure 17.4.4.1.) 1 (R): Transfer to the REMAPLEN buffer has not completed. 0 (R): Transfer to the REMAPLEN buffer has completed. Seiko Epson Corporation 17-10 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 228: Remc2 Interrupt Enable Register

    These bits set the carrier signal cycle. A carrier signal cycle begins with the 8-bit counter for carrier generation = 0x00 and ends when the counter exceeds the REMCARR.CRPER[7:0] bit-setting value. (See Figure 17.4.3.2.) Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL 17-11 (Rev. 1.2)

  • Page 229: Remc2 Carrier Modulation Control Register

    This bit enables carrier modulation. 1 (R/W): Enable carrier modulation 0 (R/W): Disable carrier modulation (output data signal only) Note: When carrier modulation is disabled, the REMDBCTL.REMOINV bit should be set to 0. Seiko Epson Corporation 17-12 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 230: Lcd Driver (Lcd8B)

    • Includes a power supply for 1/3 bias driving (allows external voltages to be applied). • Provides the frame signal monitoring output pin. • Can generate interrupts every frame. Figure 18.1.1 shows the LCD8B configuration. Table 18.1.1 LCD8B Configuration of S1C17W14/W16 Item S1C17W14 S1C17W16 Number of segments supported Max.

  • Page 231: Output Pins And External Connections

    18.3.1 LCD8B Operating Clock When using LCD8B, the LCD8B operating clock CLK_LCD8B must be supplied to LCD8B from the clock gen- erator. The CLK_LCD8B supply should be controlled as in the procedure shown below. Seiko Epson Corporation 18-2 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 232: Clock Supply In Sleep Mode

    73.1 85.3 102.4 128.0 170.7 256.0 512.0 85.3 97.5 113.8 136.5 170.7 227.6 341.3 682.7 128.0 146.3 170.7 204.8 256.0 341.3 512.0 1,024.0 256.0 292.6 341.3 409.6 512.0 682.7 1,024.0 2,048.0 Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL 18-3 (Rev. 1.2)

  • Page 233: Lcd Power Supply

    LCD voltage regulator off and the LCD8PWR.BSTEN bit to 1 to turn the LCD voltage booster on. Figure 18.4.3.1 shows an external connection example for external voltage application mode 2. LCD4 LCD2 LCD3 Figure 18.4.3.1 External Connection Example for External Voltage Application Mode 2 (when V is applied) Seiko Epson Corporation 18-4 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 234: Lcd Voltage Regulator Settings

    8. Write display data to the display data RAM. 9. Set the following bits when using the interrupt: - Write 1 to the LCD8INTF.FRMIF bit. (Clear interrupt flag) - Set the LCD8INTE.FRMIE bit to 1. (Enable LCD8B interrupt) Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL 18-5 (Rev. 1.2)

  • Page 235: Display On/Off

    RAM. Setting the LCD8DSP.DSPREV bit to 0 inverts the display; setting it to 1 returns the display to normal status. Note that the display will not be inverted when the LCD8DSP.DSPC[1:0] bits = 0x3 (All off). Seiko Epson Corporation 18-6 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 236: Drive Duty Switching

    SEG1 SEG1 SEG1 SEG1 COM6/SEG2 COM6 COM6 Unused Unused SEG2 SEG2 SEG2 SEG2 COM7/SEG3 COM7 Unused Unused Unused SEG3 SEG3 SEG3 SEG3 SEG4–53/59 SEG4–53/59 SEG4–53/59 SEG4–53/59 SEG4–53/59 SEG4–53/59 SEG4–53/59 SEG4–53/59 SEG4–53/59 Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL 18-7 (Rev. 1.2)

  • Page 237: Drive Waveforms

    1 frame LFRO display status COM0 COM0 COM1 COM2 COM3 COM1 COM4 COM5 COM6 COM7 COM2 SEGx COM3 COM4 COM5 COM6 COM7 SEGx Figure 18.5.5.1 1/8 Duty Drive Waveform (1/3 bias) Seiko Epson Corporation 18-8 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)
  • Page 238 COM2 COM3 COM1 SEGx COM2 COM3 SEGx Figure 18.5.5.2 1/4 Duty Drive Waveform (1/3 bias) 1 frame LFRO display status COM0 COM0 SEGx SEGx Figure 18.5.5.3 Static Drive Waveform (1/3 bias) Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL 18-9 (Rev. 1.2)

  • Page 239: Partial Common Output Drive

    In the display data RAM, two screen areas can be allocated and the LCD8DSP.DSPAR bit can be used to switch between the screens. Setting the LCD8DSP.DSPAR bit to 0 selects display area 0; setting to 1 selects display area 1. Seiko Epson Corporation 18-10 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 240: Segment Pin Assignment

    COM4 COM3 COM5 COM2 COM6 COM1 COM7 COM0 LCD8DSP.SEGREV · · · bit = 1 LCD8DSP.SEGREV · · · bit = 0 S1C17W16 Figure 18.6.3.1 Display Data RAM Map (1/8 duty) Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL 18-11 (Rev. 1.2)
  • Page 241 · · · COM4 COM0 Unused area (general-purpose RAM) LCD8DSP.SEGREV · · · bit = 1 LCD8DSP.SEGREV · · · bit = 0 S1C17W16 Figure 18.6.3.2 Display Data RAM Map (1/5 duty) Seiko Epson Corporation 18-12 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)
  • Page 242 COM2 COM1 COM3 COM0 Unused area (general-purpose RAM) LCD8DSP.SEGREV · · · bit = 1 LCD8DSP.SEGREV · · · bit = 0 S1C17W16 Figure 18.6.3.3 Display Data RAM Map (1/4 duty) Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL 18-13 (Rev. 1.2)
  • Page 243 Display area 1 COM0 COM0 Unused area (general-purpose RAM) LCD8DSP.SEGREV · · · bit = 1 LCD8DSP.SEGREV · · · bit = 0 S1C17W16 Figure 18.6.3.4 Display Data RAM Map (static drive) Seiko Epson Corporation 18-14 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 244: Interrupt

    Bit 7 Reserved Bits 6–4 CLKDIV[2:0] These bits select the division ratio of the LCD8B operating clock. Bits 3–2 Reserved Bits 1–0 CLKSRC[1:0] These bits select the clock source of the LCD8B. Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL 18-15 (Rev. 1.2)

  • Page 245: Lcd8B Control Register

    These bits set the frame frequency. For more information, refer to “Frame Frequency.” Bits 7–3 Reserved Bits 2–0 LDUTY[2:0] These bits set the drive duty. For more information, refer to “Drive Duty Switching.” Seiko Epson Corporation 18-16 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 246: Lcd8B Power Control Register

    This bit turns the LCD voltage booster on and off. 1 (R/W): LCD voltage booster on 0 (R/W): LCD voltage booster off For more information, refer to “LCD Power Supply.” Bit 3 Reserved Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL 18-17 (Rev. 1.2)

  • Page 247: Lcd8B Display Control Register

    0 (R/W): Inverted display Bit 3 Reserved Bit 2 DSPAR This bit switches the display area in the display data RAM. 1 (R/W): Display area 1 0 (R/W): Display area 0 Seiko Epson Corporation 18-18 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 248: Lcd8B Com Pin Control Register 0

    LCD8INTE 15–8 – 0x00 – – 7–1 – 0x00 – FRMIE Bits 15–1 Reserved Bit 0 FRMIE This bit enables the frame interrupt. 1 (R/W): Enable interrupt 0 (R/W): Disable interrupt Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL 18-19 (Rev. 1.2)

  • Page 249: F Converter (Rfc)

    • Provides an output and continuous oscillation function for monitoring the oscillation frequency. • Can generate reference oscillation completion, sensor (A and B) oscillation completion, measurement counter overflow error, and time base counter overflow error interrupts. Figure 19.1.1 shows the RFC configuration. Table 19.1.1 RFC Channel Configuration of S1C17W14/W16 Item S1C17W14 S1C17W16 Number of channels 1 channel (Ch.0)

  • Page 250: Input/Output Pins And External Connections

    Figure 19.2.2.1 Connection Example in Resistive Sensor DC Oscillation Mode SENBn SEN1 SENAn REFn RFINn : Reference resistor : Resistive sensor (AC bias) SEN1 S1C17 RFC : Reference capacitor Figure 19.2.2.2 Connection Example in Resistive Sensor AC Oscillation Mode Seiko Epson Corporation 19-2 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 251: Clock Settings

    (Clear interrupt flags) - Set the interrupt enable bits in the RFCnINTE register to 1. (Enable interrupts) 3. Assign the RFC input/output function to the ports. (Refer to the “I/O Ports” chapter.) Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL 19-3 (Rev. 1.2)

  • Page 252: Operating Modes

    To obtain the difference between the reference oscillation and sensor oscillation clock count values from the measurement counter simply, appropriate initial values must be set to the measurement counter before starting reference oscillation. Seiko Epson Corporation 19-4 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 253: Converting Operations And Control Procedure

    The measurement counter overflow sets the RFCnINTF.EREFIF bit to 1 indicating that the reference oscil- lation has been terminated normally. If the RFCnINTE.EREFIE bit = 1, a reference oscillation completion interrupt request occurs at this point. Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL 19-5 (Rev. 1.2)
  • Page 254 Performing reference oscillation and sensor oscillation with the same resistor and capacitor results n ≈ m. The difference between n and m is a conversion error. Table 19.4.4.1 lists the error factors. (n: measurement counter initial value, m: measurement counter value at the end of sensor oscillation) Seiko Epson Corporation 19-6 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 255: Cr Oscillation Frequency Monitoring Function

    For more information on interrupt control, refer to the “Interrupt Controller” chapter. Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL 19-7 (Rev. 1.2)

  • Page 256: Control Registers

    This bit sets the RFCLKOn pin to output the divided-by-two oscillation clock. 1 (R/W): Divided-by-two clock output 0 (R/W): Oscillation clock output For more information, refer to “CR Oscillation Frequency Monitoring Function.” Seiko Epson Corporation 19-8 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 257: Rfc Ch.n Oscillation Trigger Register

    This bit controls CR oscillation for sensor A. This bit also indicates the CR oscillation status. 1 (W): Start oscillation 0 (W): Stop oscillation 1 (R): Being oscillated 0 (R): Stopped Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL 19-9 (Rev. 1.2)

  • Page 258: Rfc Ch.n Measurement Counter Low And High Registers

    Note: The time base counter must be set from the low-order value (RFCnTCL.TC[15:0] bits) first when data is set using a 16-bit access instruction. The counter may not be set to the correct value if the high-order value (RFCnTCH.TC[23:16] bits) is written first. Seiko Epson Corporation 19-10 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 259: Rfc Ch.n Interrupt Flag Register

    RFCnINTE.OVTCIE bit: Time base counter overflow error interrupt RFCnINTE.OVMCIE bit: Measurement counter overflow error interrupt RFCnINTE.ESENBIE bit: Sensor B oscillation completion interrupt RFCnINTE.ESENAIE bit: Sensor A oscillation completion interrupt RFCnINTE.EREFIE bit: Reference oscillation completion interrupt Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL 19-11 (Rev. 1.2)

  • Page 260: 12-Bit A/D Converter (Adc12A)

    2. 16-bit timer underflow trigger 3. External trigger • Can convert multiple analog input signals sequentially. • Can generate conversion completion and overwrite error interrupts. Figure 20.1.1 shows the ADC12A configuration. Table 20.1.1 ADC12A Configuration of S1C17W14/W16 Item S1C17W14 S1C17W16 Number of channels –...

  • Page 261: Input Pins And External Connections

    : acquisition time). Figure 20.3.2.1 shows an equivalent circuit of the analog input portion. ADINnm ADIN ADIN Source impedance : Analog input resistance ADIN : Analog input capacitance ADIN Figure 20.3.2.1 Equivalent Circuit of Analog Input Portion Seiko Epson Corporation 20-2 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 262: Operations

    A/D conversion is actually started in sync with CLK_T16_k after a trigger is accepted. Writing 0 to the ADC12_nCTL.ADST bit stops A/D conversion after the one currently being executed has com- pleted. Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL 20-3 (Rev. 1.2)

  • Page 263: Conversion Mode And Analog Input Pin Settings

    3. Read the A/D conversion result of the analog input m (ADC12_nADmD.ADmD[15:0] bits). 4. Repeat Steps 2 and 3 until terminating A/D conversion. 5. Write 0 to the ADC12_nCTL.ADST bit. The ADC12A stops operating after the A/D conversion currently being executed has completed. Seiko Epson Corporation 20-4 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)
  • Page 264 ADINn4 ADINn4 ADC12_nAD3D.AD3D[15:0] ADINn3 conversion result (first) ADINn3 conversion result (second) ADC12_nAD4D.AD4D[15:0] ADINn4 conversion result (first) ADINn4 conversion result (second) Cleared Cleared ADC12_nINTF.AD3CIF Cleared Cleared ADC12_nINTF.AD4CIF Figure 20.4.4.1 A/D Conversion Operations Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL 20-5 (Rev. 1.2)

  • Page 265: Interrupts

    (ADC12_nTRG.CNVMD = 0). If A/D conversion is stopped after the maximum analog input pin number (different in each model) has been completed, these bits indicate ADINn0. Bit 11 Reserved Seiko Epson Corporation 20-6 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 266: Adc12A Ch.n Trigger/Analog Input Select Register

    ENDAIN[2:0] bits ≥ ADC12_nTRG.STAAIN[2:0] bits. Bits 10–8 STAAIN[2:0] These bits set the analog input pin to be A/D converted first. See Table 20.6.1 for the relationship between analog input pins and bit setting values. Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL 20-7 (Rev. 1.2)

  • Page 267: Adc12A Ch.n Configuration Register

    Note: Make sure that the ADC12_nCTL.BSYSTAT bit is set to 0 before altering the ADC12_nCFG register. Bits 15–2 Reserved Bits 1–0 VRANGE[1:0] These bits set the A/D converter operating voltage range. Seiko Epson Corporation 20-8 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 268: Adc12A Ch.n Interrupt Flag Register

    The following shows the correspondence between the bit and interrupt: ADC12_nINTF.ADmOVIF bit: Analog input signal m A/D conversion result overwrite error interrupt ADC12_nINTF.ADmCIF bit: Analog input signal m A/D conversion completion interrupt Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL 20-9 (Rev. 1.2)

  • Page 269: Adc12A Ch.n Interrupt Enable Register

    ADC12A Ch.n Result Register m Register name Bit name Initial Reset Remarks ADC12_nADmD 15–0 ADmD[15:0] 0x0000 – Bits 15–0 ADmD[15:0] These bits are the A/D conversion results of the analog input signal m. Seiko Epson Corporation 20-10 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 270: Multiplier/Divider (Copro2)

    %rs[6:0] is written to the mode setting register. (%rd: not used) ld.cw %rd,%rs imm7[6:0] is written to the mode setting register. (%rd: not used) ld.cw %rd,imm7 Output mode setting value Operation mode setting value Figure 21.2.1 Mode Setting Register Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL 21-1 (Rev. 1.2)

  • Page 271: Multiplication

    16 bits Argument 1 32 bits Operation result S1C17 Core Operation result Operation result register 1 register 0 Selector Coprocessor output (16 bits) Flag output Figure 21.3.1 Data Path in Multiplication Mode Seiko Epson Corporation 21-2 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 272: Division

    16 bits Argument 1 32 bits Operation result S1C17 Core Operation result Operation result register 1 register 0 Selector Coprocessor output Flag output Figure 21.4.1 Data Path in Initialize Mode 2 Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL 21-3 (Rev. 1.2)
  • Page 273 %rd ← res1[31:16] (Remainder) (ext imm9) res0[31:0] ÷ {%rd, imm7/16} ld.ca %rd,imm7 res0[31:0] ← Quotient res1[31:0] ← Remainder %rd ← res1[31:16] (Remainder) res0: operation result register 0, res1: operation result register 1 Seiko Epson Corporation 21-4 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 274: Mac

    COPRO2 Argument 2 16 bits Argument 1 32 bits S1C17 Core Operation result Operation result register 1 register 0 Selector Coprocessor output Flag output Figure 21.5.1 Data Path in Initialize Mode Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL 21-5 (Rev. 1.2)
  • Page 275 %r0. ld.cw %r0,0x13 ; Sets the mode (operation result read mode and 16 high-order bits output mode 0). ; Loads the 16 high-order bits of the result to %r1. ld.ca %r1,%r0 Seiko Epson Corporation 21-6 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 276: Reading Operation Results

    %rd,%rs 0x23 %rd ← res1[15:0] ld.ca %rd,imm7 %rd ← res1[15:0] ld.ca %rd,%rs 0x33 %rd ← res1[31:16] ld.ca %rd,imm7 %rd ← res1[31:16] res0: operation result register 0, res1: operation result register 1 Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL 21-7 (Rev. 1.2)

  • Page 277: Electrical Characteristics

    *5 R is not required when using the DSIO pin as a general-purpose I/O port. *6 The component values should be determined after evaluating operations using an actual mounting board. Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL 22-1 (Rev. 1.2)

  • Page 278: Current Consumption

    SYSCLK = OSC3, running in the RAM *1 OSC1 oscillator: CLGOSC1.INV1N[1:0] bits = 0x0, CLGOSC1.CGI1[2:0] bits = 0x0, CLGOSC1.OSDEN bit = 0, = 0 pF, Crystal resonator = C-002RX (manufactured by Seiko Epson Corporation, R = 50 kW (Max.), C = 7 pF) *2 OSC3 oscillator: CLGOSC3.OSC3MD[1:0] bits = 0x2, CLGOSC3.OSC3INV[1:0] bits = 0x0, C...
  • Page 279 RUN mode (OSC3 operation) IOSC = OFF, OSC1 = 32 kHz, OSC3 = ON, Ta = 25 °C, Typ. value 1,000 Run in Flash Run in RAM Internal oscillator Ceramic oscillator [MHz] OSC3 Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL 22-3 (Rev. 1.2)

  • Page 280: System Reset Controller (Src) Characteristics

    Oscillation start time – – µs Oscillation frequency 25 °C 1.6 to 3.6 V IOSC 1.2 to 1.6 V 1.6 to 3.6 V -40 to 85 °C 1.2 to 1.6 V Seiko Epson Corporation 22-4 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)
  • Page 281 CLGOSC1.OSDEN bit = 1 – 0.025 µA OSD1 *1 CLGOSC1.CGI1[2:0] bits = 0x0, Crystal resonator = C-002RX (manufactured by Seiko Epson Corporation, R = 50 kW (Max.), C = 7 pF) OSC3 oscillator circuit characteristics Unless otherwise specified: V = 1.2 to 3.6 V, V = 0 V, Ta = 25 °C...
  • Page 282 0.8 × V Low level Schmitt input threshold voltage 0.2 × V – 0.5 × V Schmitt input hysteresis voltage – – = 1/f = 1/f EXOSC EXOSC EXOSC EXOSC EXOSCH EXOSCH EXOSC Seiko Epson Corporation 22-6 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 283: Flash Memory Characteristics

    Ta = 85 °C, Min. value –V = 1.2 V = 3.6 V = 1.6 V = 1.6 V = 1.2 V 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 = 3.6 V Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL 22-7 (Rev. 1.2)
  • Page 284 3.49 SVDCTL.SVDC[4:0] bits = 0x1d 3.41 3.50 3.59 SVDCTL.SVDC[4:0] bits = 0x1e 3.51 3.60 3.69 SVD circuit enable response time – – µs SVDEN SVD circuit response time – – µs Seiko Epson Corporation 22-8 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 285: Uart (Uart) Characteristics

    Transfer baud rate Normal mode 1.6 to 3.6 V – 230,400 BRT1 1.2 to 1.6 V – 57,600 IrDA mode 1.6 to 3.6 V – 115,200 BRT2 1.2 to 1.6 V – 57,600 Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL 22-9 (Rev. 1.2)

  • Page 286: Synchronous Serial Interface (Spia) Characteristics

    (CPOL, CPHA) = (1, 0) or (0, 1) SPICLKn (CPOL, CPHA) = (1, 1) or (0, 0) SDIn SDOn Slave mode #SPISSn SPICLKn (CPOL, CPHA) = (0, 1) SPICLKn (CPOL, CPHA) = (1, 0) SDIn Hi-Z SDOn Seiko Epson Corporation 22-10 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 287: I 2 C (I2C) Characteristics

    3.14 3.24 3.34 LCD8PWR.LC[3:0] bits = 0xc 3.20 3.30 3.40 LCD8PWR.LC[3:0] bits = 0xd 3.26 3.36 3.46 LCD8PWR.LC[3:0] bits = 0xe 3.32 3.42 3.52 LCD8PWR.LC[3:0] bits = 0xf 3.38 3.48 3.58 Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL 22-11 (Rev. 1.2)
  • Page 288 V and V (no panel load) is connected between V and V (no panel load) LCD8PWR.LC[3:0] bits = 0xf LCD8PWR.LC[3:0] bits = 0xf LCD8PWR.LC[3:0] bits = 0x0 LCD8PWR.LC[3:0] bits = 0x0 Seiko Epson Corporation 22-12 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 289: R/F Converter (Rfc) Characteristics

    = 100 kW, – µA Ta = 25 °C, V = 3.6 V *1 In this characteristic, unevenness between production lots, and variations in measurement board, resistances and capacitances are taken into account. Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL 22-13 (Rev. 1.2)
  • Page 290 = 1,000 pF, Ta = 25 °C, Typ. value 1,800 1,600 = 3.6 V 1,400 1.6 V 1,200 1.2 V 1,000 = 3.6 V 1.6 V 1.2 V 1,000 Ta [°C] [kHz] RFCLK Seiko Epson Corporation 22-14 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 291: 12-Bit A/D Converter (Adc12A) Characteristics

    , ADIN = V /2, f = 50 ksps, Ta = 25 °C, Typ. value REFA REFA 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 REFA Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL 22-15 (Rev. 1.2)

  • Page 292: Basic External Connection Diagram

    UART USOUTn TOUTn0/CAPn0 PWM/Capture TOUTn1/CAPn1 *1: For Flash programming *2: When OSC3 CR oscillator is selected *3: When OSC3 crystal/ceramic oscillator is selected ( ): Do not mount components if unnecessary. Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL 23-1 (Rev. 1.2)
  • Page 293 A/D conversion inputs #ADTRG0 VREFA0 *1: For Flash programming *2: When OSC3 CR oscillator is selected *3: When OSC3 crystal/ceramic oscillator is selected ( ): Do not mount components if unnecessary. Seiko Epson Corporation 23-2 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)
  • Page 294 Symbol Name Recommended components X'tal1 32 kHz crystal resonator C-002RX (R = 50 kW (Max.), C = 7 pF) manufactured by Seiko Epson Corporation OSC1 gate capacitor Trimmer capacitor or ceramic capacitor OSC1 drain capacitor Ceramic capacitor X’tal3 Crystal resonator...

  • Page 295: Package

    24 PACKAGE 24 Package QFP15-100PIN (P-LQFP100-1414-0.50) (Unit: mm) INDEX 0.17 /0.27 0.09 /0.2 0° /10° /0.75 Figure 24.1 QFP15-100PIN Package Dimensions Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL 24-1 (Rev. 1.2)
  • Page 296 24 PACKAGE TQFP15-128PIN (P-TQFP128-1414-0.40) (Unit: mm) INDEX 0.13 /0.23 0.09 /0.2 0° /10° /0.75 Figure 24.2 TQFP15-128PIN Package Dimensions Seiko Epson Corporation 24-2 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 297: Appendix A List Of Peripheral Circuit Control Registers

    WUPMD R/WP – (CLG System Clock – – Control Register) 13–12 WUPDIV[1:0] R/WP 11–10 – – 9–8 WUPSRC[1:0] R/WP 7–6 – – 5–4 CLKDIV[1:0] R/WP 3–2 – – 1–0 CLKSRC[1:0] R/WP Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL AP-A-1 (Rev. 1.2)
  • Page 298 – – Register) (reserved) OSC1STPIE IOSCTEDIE – – OSC3STAIE OSC1STAIE IOSCSTAIE 0x4050 CLGFOUT 15–8 – 0x00 – – (CLG FOUT Control – – Register) 6–4 FOUTDIV[2:0] 3–2 FOUTSRC[1:0] – – FOUTEN Seiko Epson Corporation AP-A-2 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)
  • Page 299 15–11 – 0x00 – – (ITC Interrupt Level 10–8 ILV17[2:0] R/F converter Ch.1 interrupt Setup Register 8) (ILVRFC_1) (S1C17W16 only) 7–3 – 0x00 – – 2–0 ILV16[2:0] R/F converter Ch.0 interrupt (ILVRFC_0) Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL AP-A-3 (Rev. 1.2)
  • Page 300 – – RTCADJ Cleared by setting the RTCCTL.RTCRST bit to 1. RTCRST – RTCRUN 0x40c2 RTCALM1 – – – (RTC Second Alarm 14–12 RTCSHA[2:0] Register) 11–8 RTCSLA[3:0] 7–0 – 0x00 – Seiko Epson Corporation AP-A-4 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)
  • Page 301 0x40d0 RTCINTF RTCTRMIF Cleared by writing 1. (RTC Interrupt Flag SW1IF Register) SW10IF SW100IF 11–9 – – – ALARMIF Cleared by writing 1. 1DAYIF 1HURIF 1MINIF 1SECIF 1_2SECIF 1_4SECIF 1_8SECIF 1_32SECIF Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL AP-A-5 (Rev. 1.2)
  • Page 302 15–8 – 0x00 – – (T16 Ch.0 Mode 7–1 – 0x00 – Register) TRMD 0x4164 T16_0CTL 15–9 – 0x00 – – (T16 Ch.0 Control PRUN Register) 7–2 – 0x00 – PRESET MODEN Seiko Epson Corporation AP-A-6 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 303: 0X41B0 Flash Controller (Flashc)

    (P0 Port Function 13–12 P06MUX[1:0] Select Register) 11–10 P05MUX[1:0] 9–8 P04MUX[1:0] 7–6 P03MUX[1:0] 5–4 P02MUX[1:0] 3–2 P01MUX[1:0] 1–0 P00MUX[1:0] 0x4210 P1DAT 15–8 P1OUT[7:0] 0x00 – (P1 Port Data 7–0 P1IN[7:0] 0x00 Register) Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL AP-A-7 (Rev. 1.2)
  • Page 304 (P2 Port Chattering 7–6 – – Filter Enable Register) 5–0 P2CHATEN[5:0] 0x00 S1C17W16 0x422c P2MODSEL 15–8 – 0x00 – – (P2 Port Mode Select 7–6 – – Register) 5–0 P2SEL[5:0] 0x00 S1C17W16 Seiko Epson Corporation AP-A-8 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)
  • Page 305 (P4 Port Enable 12–8 P4IEN[4:0] 0x00 Register) 7–5 – – S1C17W16 4–0 P4OEN[4:0] 0x00 0x4244 P4RCTL 15–12 – – – (P4 Port Pull-up/down 11–8 P4PDPU[3:0] Control Register) 7–4 – – S1C17W14 3–0 P4REN[3:0] Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL AP-A-9 (Rev. 1.2)
  • Page 306 Select Register) 7–6 P43MUX[1:0] S1C17W16 5–4 P42MUX[1:0] 3–2 P41MUX[1:0] 1–0 P40MUX[1:0] 0x42d0 PDDAT 15–13 – – – (Pd Port Data 12–8 PDOUT[4:0] Register) 7–5 – – 4–3 PDIN[4:3] – – 1–0 PDIN[1:0] Seiko Epson Corporation AP-A-10 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 307: 0X4300-0X431E Universal Port Multiplexer (Upmux)

    10–8 P01PERISEL[2:0] Setting Register) 7–5 P00PPFNC[2:0] 4–3 P00PERICH[1:0] 2–0 P00PERISEL[2:0] 0x4302 P0UPMUX1 15–13 P03PPFNC[2:0] – (P02–03 Universal 12–11 P03PERICH[1:0] Port Multiplexer 10–8 P03PERISEL[2:0] Setting Register) 7–5 P02PPFNC[2:0] 4–3 P02PERICH[1:0] 2–0 P02PERISEL[2:0] Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL AP-A-11 (Rev. 1.2)
  • Page 308 Setting Register) 7–5 P22PPFNC[2:0] S1C17W16 4–3 P22PERICH[1:0] 2–0 P22PERISEL[2:0] 0x4314 P2UPMUX2 15–13 P25PPFNC[2:0] – (P24–25 Universal 12–11 P25PERICH[1:0] Port Multiplexer 10–8 P25PERISEL[2:0] Setting Register) 7–5 P24PPFNC[2:0] S1C17W16 4–3 P24PERICH[1:0] 2–0 P24PERISEL[2:0] Seiko Epson Corporation AP-A-12 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 309: 0X4380-0X438E Uart (Uart) Ch.0

    MODEN 0x4388 UA0TXD 15–8 – 0x00 – – (UART Ch.0 Transmit 7–0 TXD[7:0] 0x00 Data Register) 0x438a UA0RXD 15–8 – 0x00 – – (UART Ch.0 Receive 7–0 RXD[7:0] 0x00 Data Register) Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL AP-A-13 (Rev. 1.2)
  • Page 310 (T16 Ch.1 Interrupt 7–1 – 0x00 – Flag Register) UFIF Cleared by writing 1. 0x43ac T16_1INTE 15–8 – 0x00 – – (T16 Ch.1 Interrupt 7–1 – 0x00 – Enable Register) UFIE Seiko Epson Corporation AP-A-14 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 311: 0X43C0-0X43D2 I

    0x43c4 I2C0BR 15–8 – 0x00 – – (I2C Ch.0 Baud-Rate – – Register) 6–0 BRT[6:0] 0x7f 0x43c8 I2C0OADR 15–10 – 0x00 – – (I2C Ch.0 Own 9–0 OADR[9:0] 0x000 Address Register) Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL AP-A-15 (Rev. 1.2)
  • Page 312 (T16B Ch.0 Clock DBRUN Control Register) 7–4 CLKDIV[3:0] – – 2–0 CLKSRC[2:0] 0x5002 T16B0CTL 15–9 – 0x00 – – (T16B Ch.0 Counter MAXBSY Control Register) 7–6 – – 5–4 CNTMD[1:0] ONEST PRESET MODEN Seiko Epson Corporation AP-A-16 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)
  • Page 313 14–12 CBUFMD[2:0] Capture 1 Control 11–10 CAPIS[1:0] Register) 9–8 CAPTRG[1:0] – – TOUTMT TOUTO 4–2 TOUTMD[2:0] TOUTINV CCMD 0x501a T16B0CCR1 15–0 CC[15:0] 0x0000 – (T16B Ch.0 Compare/ Capture 1 Data Register) Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL AP-A-17 (Rev. 1.2)
  • Page 314 14–12 CBUFMD[2:0] Capture 0 Control 11–10 CAPIS[1:0] Register) 9–8 CAPTRG[1:0] – – TOUTMT TOUTO 4–2 TOUTMD[2:0] TOUTINV CCMD 0x5052 T16B1CCR0 15–0 CC[15:0] 0x0000 – (T16B Ch.1 Compare/ Capture 0 Data Register) Seiko Epson Corporation AP-A-18 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)
  • Page 315 MODEN 0x5208 UA1TXD 15–8 – 0x00 – – (UART Ch.1 Transmit 7–0 TXD[7:0] 0x00 Data Register) 0x520a UA1RXD 15–8 – 0x00 – – (UART Ch.1 Receive 7–0 RXD[7:0] 0x00 Data Register) Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL AP-A-19 (Rev. 1.2)
  • Page 316 (T16 Ch.2 Interrupt 7–1 – 0x00 – Flag Register) UFIF Cleared by writing 1. 0x526c T16_2INTE 15–8 – 0x00 – – (T16 Ch.2 Interrupt 7–1 – 0x00 – Enable Register) UFIE Seiko Epson Corporation AP-A-20 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)
  • Page 317 0x5284 T16_3CTL 15–9 – 0x00 – – (T16 Ch.3 Control PRUN Register) 7–2 – 0x00 – S1C17W16 PRESET MODEN 0x5286 T16_3TR 15–0 TR[15:0] 0xffff – (T16 Ch.3 Reload Data Register) S1C17W16 Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL AP-A-21 (Rev. 1.2)

  • Page 318: 0X5290-0X529A Synchronous Serial Interface (Spia) Ch.2 (S1C17W16 Only)

    SPI2RXD register. TBEIF H0/S0 Cleared by writing to the SPI2TXD register. 0x529a SPI2INTE 15–8 – 0x00 – – (SPIA Ch.2 Interrupt 7–4 – – Enable Register) OEIE S1C17W16 TENDIE RBFIE TBEIE Seiko Epson Corporation AP-A-22 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)
  • Page 319 Cleared by writing 1 to the REMDBCTL.REMCRST bit. (REMC2 Data Bit Counter Register) 0x5326 REMAPLEN 15–0 APLEN[15:0] 0x0000 Writing enabled when REM- DBCTL.MODEN bit = 1. (REMC2 Data Bit Active Pulse Length Register) Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL AP-A-23 (Rev. 1.2)
  • Page 320 9–8 BSTC[1:0] Control Register 2) 7–3 – 0x00 – 2–0 NLINE[2:0] 0x5408 LCD8PWR 15–12 – – – (LCD8B Power 11–8 LC[3:0] Control Register) 7–5 – – BSTEN – – HVLD VCSEL VCEN Seiko Epson Corporation AP-A-24 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)
  • Page 321 0x5448 RFC0MCH 15–8 – 0x00 – – (RFC Ch.0 Measure- ment Counter High 7–0 MC[23:16] 0x00 Register) 0x544a RFC0TCL 15–0 TC[15:0] 0x0000 – (RFC Ch.0 Time Base Counter Low Regis- ter) Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL AP-A-25 (Rev. 1.2)
  • Page 322 0x546a RFC1TCL 15–0 TC[15:0] 0x0000 – (RFC Ch.1 Time Base Counter Low Register) S1C17W16 0x546c RFC1TCH 15–8 – 0x00 – – (RFC Ch.1 Time Base 7–0 TC[23:16] 0x00 Counter High Register) S1C17W16 Seiko Epson Corporation AP-A-26 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)
  • Page 323 (T16 Ch.4 Interrupt 7–1 – 0x00 – Flag Register) UFIF Cleared by writing 1. S1C17W16 0x548c T16_4INTE 15–8 – 0x00 – – (T16 Ch.4 Interrupt 7–1 – 0x00 – Enable Register) UFIE S1C17W16 Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL AP-A-27 (Rev. 1.2)
  • Page 324 15–0 AD1D[15:0] 0x0000 – (ADC12A Ch.0 Result Register 1) 0x54b0 ADC12_0AD2D 15–0 AD2D[15:0] 0x0000 – (ADC12A Ch.0 Result Register 2) 0x54b2 ADC12_0AD3D 15–0 AD3D[15:0] 0x0000 – (ADC12A Ch.0 Result Register 3) Seiko Epson Corporation AP-A-28 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 325: 0Xffff90

    APPENDIX A LIST OF PERIPHERAL CIRCUIT CONTROL REGISTERS 0xffff90 Debugger (DBG) Address Register name Bit name Initial Reset Remarks 0xffff90 DBRAM 31–24 – 0x00 – – (Debug RAM Base 23–0 DBRAM[23:0] 0x00 Register) 0fc0 Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL AP-A-29 (Rev. 1.2)

  • Page 326: Appendix B Power Saving

    • Using a crystal resonator with lower C value decreases current consumption. However, these configurations may reduce the oscillation margin and increase the frequency error, therefore, be sure to perform matching evaluation using the actual printed circuit board. Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL AP-B-1 (Rev. 1.2)

  • Page 327: Other Power Saving Methods

    • Setting the LCD voltage regulator into heavy load protection mode (LCD8PWR.HVLD bit = 1) increases current consumption. Heavy load protection mode should be set only when the display becomes unstable. Seiko Epson Corporation AP-B-2 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 328: Appendix C Mounting Precautions

    Sudden power supply fluctuations due to noise will cause malfunctions. Consider the following issues. (1) Connections from the power supply to the V and V pins should be implemented via the shortest, thick- est patterns possible. Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL AP-C-1 (Rev. 1.2)
  • Page 329 (2) Electromagnetically-induced noise from a solder iron when soldering In particular, during soldering, take care to ensure that the soldering iron GND (tip potential) has the same po- tential as the IC GND. Seiko Epson Corporation AP-C-2 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 330: Appendix D Measures Against Noise

    • Execute the resending process via software after executing the receive error handler with a parity check. For details of the pin functions and the function switch control, see the “I/O Ports” chapter. For the UART con- trol and details of receive errors, see the “UART” chapter. Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL AP-D-1 (Rev. 1.2)

  • Page 331: Appendix E Initialization Routine

    %r1, 0x41b0 ; FLASHC register address ; Flash read wait cycle Xld.a %r0, 0x00 ; 0x00 = No wait ...(5) ld.b [%r1], %r0 ; [0x41b0] <= 0x00 ; ===== Main routine ========================================= Seiko Epson Corporation S1C17W14/W16 TECHNICAL MANUAL AP-E-1 (Rev. 1.2)
  • Page 332 “intXX_handler” can be used for software interrupts. (3) The program code is written in the “.text” section. (4) Sets the stack pointer. (5) Sets the number of Flash memory read cycles. (See the “Memory and Bus” chapter.) Seiko Epson Corporation AP-E-2 S1C17W14/W16 TECHNICAL MANUAL (Rev. 1.2)

  • Page 333: Revision History

    REVISION HISTORY Revision History Code No. Page Contents rev1.0 New establishment 412910300 2-21 Power Supply, Reset, and Clocks: CLG OSC3 Control Register Modified the register table (OSC3WT[2:0]: Initial = 0x6 → 0x0) WDT: WDT Operating Clock (Old) Use the following equation to calculate the WDT counter overflow cycle (NMI/reset generation cycle).
  • Page 334 (New) Note: After the data signal is output in one-shot mode, set the REMDBCTL.REMCRST bit to 1. 23-3 Basic External Connection Diagram: Sample external components (Old) X’tal3 | Crystal resonator | CA-301 (1 MHz) manufactured by Seiko Epson Corporation (New) X’tal3 | Crystal resonator | CA-301 (4 MHz) manufactured by Seiko Epson Corporation AP-A-2 List of Peripheral Circuit Control Registers: CLG OSC3 Control Register Modified the register table (OSC3WT[2:0]: Initial = 0x6 →...
  • Page 335 REVISION HISTORY Code No. Page Contents 412910301 8.4 Control Registers WDT Control Register Corrected the description of the WDTRUN[3:0] bits. Bits 3–0 WDTRUN[3:0] These bits control WDT to run and stop. 0xa (WP): Stop Values other than 0xa (WP): Run 0xa (R): Idle 0x0 (R):...
  • Page 336 Code No. Page Contents 412910301 18-4 18.4.3 External Voltage Application Mode 2 Corrected the description. In this mode, the LCD drive voltage V or V is applied from outside the IC and other voltages are internally generated. 18-6 18.5.2 Display On/Off Added a note.
  • Page 337 Phone: +86-755-3299-0588 Fax: +86-755-3299-0560 Epson Europe Electronics GmbH Riesstrasse 15, 80992 Munich, Germany Epson Taiwan Technology & Trading Ltd. Phone: +49-89-14005-0 Fax: +49-89-14005-110 15F, No. 100, Songren Rd, Sinyi Dist, Taipei City 110, Taiwan Phone: +886-2-8786-6688 Epson Singapore Pte., Ltd.

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