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5.2. Vector Table
The vector table contains the vectors to the interrupt handler routines (handler routine start address)
that will be read by the CPU to execute the handler when an interrupt occurs.
Table 5.2.1 shows the vector table.
VTOR initial value = 0x0
Interrupt
IRQ
Vector
number
number
address
offset
0
-
0x00
1
-
0x04
2
NMI
0x08
3
-
0x0c
4
-
0x10
5
-
0x14
6
-
0x18
7
-
0x1c
8
-
0x20
9
-
0x24
10
-
0x28
11
-
0x2c
12
-
0x30
13
-
0x34
14
-
0x38
15
-
0x3c
16
0
0x40
17
1
0x44
18
2
0x48
19
3
0x4c
20
4
0x50
21
5
0x54
22
6
0x58
23
7
0x5c
5-2
Table 5.2.1 Vector Table
Source
Hardware interrupt name
-
Stack pointer initial value
Reset
WDT
NMI
CPU
Hard fault
-
System Reserved
-
System Reserved
-
System Reserved
-
System Reserved
-
System Reserved
-
System Reserved
-
System Reserved
CPU
SV call
-
System Reserved
-
System Reserved
CPU
PendSV
Sys Tick
DMA
DMA controller interrupt
SVD
Supply voltage detector
interrupt
PORT01
Port01 interrupt
PORT23
Port23 interrupt
PPORTothers
PortOthers interrupt
CLG
Clock generator interrupt
RTC
Real-time clock interrupt
HW
HW Proceesor interrupt
Proceesor
Seiko Epson Corporation
Cause of hardware interrupt
-
• Low input to the #RESET pin
• Power-on reset
• Key reset
• Watchdog timer overflow *1
• Supply voltage detector reset
Watchdog timer overflow *1
• Bus error
• Undefined instruction
• Unaligned address etc
-
-
-
-
-
-
-
SVC instruction
-
-
-
SysTick timer underflow
Transfer complete
Transfer error
Power supply voltage drop
detection
Port01 input
Port23 input
PortOthers input
IOSC oscillation stabilization
waiting completion
OSC1 oscillation stabilization
waiting completion
OSC3 oscillation stabilization
waiting completion
OSC1 oscillation stop detection
OSC3 oscillation auto-trimming
completion
• 1-day, 1-hour, 1-minute, and 1-
second
• 1/32-second, 1/8-second, 1/4-
second, and 1/2-second
• Stopwatch 1 Hz, 10 Hz, and 100
Hz
• Alarm
• Theoretical regulation
completion
S1C31D50 TECHNICAL MANUAL
Priority
-
3
-
1
-
-
-
-
-
-
-
Configurable
-
-
Configurable
(Rev. 1.00)
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