Epson S1C17M10 Instruction Manual

S1C17M10
■ DESCRIPTIONS
The S1C17M10 is a 16-bit embedded Flash MCU that features low power consumption. It includes various serial inter-
faces and an LCD driver on the compact die, and is ideal for battery-driven electronic equipment such as smart card
read type eTokens and remote control units with a high-definition LCD display.
■ FEATURES
Model
CPU
CPU core
Other
Embedded Flash memory
Capacity
Erase/program count
Other
Embedded RAM
Capacity
Embedded display RAM
Capacity
Clock generator (CLG)
System clock source
System clock frequency (operating frequency) 16.8 MHz (max.)
IOSC oscillator circuit (boot clock source)
OSC1 oscillator circuit
OSC3 oscillator circuit
EXOSC clock input
Other
I/O port (PPORT)
Number of general-purpose I/O ports
Number of input interrupt ports
Number of ports that support universal port
multiplexer (UPMUX)
Timers
Watchdog timer (WDT2)
Real-time clock (RTCA)
16-bit timer (T16)
(rev1.1)
16-bit Single Chip Microcontroller
● Smart card Interface (ISO7816-3) is embedded.
● 64KB Flash ROM: Read/program protection function, 4KB RAM
● Supports 1.8V to 5.5V wide range operating voltage.
● Equipped with an LCD driver capable of driving an 80 SEG × 16 COM
/ 88 SEG × 8 COM LCD panel.
● Supports various kinds of interfaces (UART, SPI, I
Seiko Epson original 16-bit RISC CPU core S1C17
On-chip debugger
64K bytes (for both instructions and data)
1,000 times (min.) * Programming by the debugging tool ICDmini
Security function to protect from reading/programming by ICDmini
On-board programming function using ICDmini
Flash programming voltage can be generated internally.
4K bytes
352 bytes
4 sources (IOSC/OSC1/OSC3/EXOSC)
700 kHz (typ.) embedded oscillator
23 µs (max.) starting time (time from cancelation of SLEEP state to vector table read by
the CPU)
32.768 kHz (typ.) crystal oscillator
32 kHz (typ.) embedded oscillator
Oscillation stop detection circuit included
16.8 MHz (max.) crystal/ceramic oscillator
4, 8, 12, and 16 MHz-switchable embedded oscillator
Auto-trimming function for the embedded oscillator
16.8 MHz (max.) square or sine wave input
Configurable system clock division ratio
Configurable system clock used at wake up from SLEEP state
Operating clock frequency for the CPU and all peripheral circuits is selectable.
Input/output port: 32 bits (max.)
Output port: 1 bit (max.)
Pins are shared with the peripheral I/O.
28 bits (max.)
28 bits
A peripheral circuit I/O function selected via software can be assigned to each port.
Generates NMI or watchdog timer reset.
Programmable NMI/reset generation cycle
128–1 Hz counter, second/minute/hour/day/day of the week/month/year counters
Theoretical regulation function for 1-second correction
Alarm and stopwatch functions
5 channels
Generates the SPIA master clock.
2 C)
S1C17M10