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15.5.4. Data Transmission in Master Mode
A data sending procedure and operations in master mode are shown below. Figures 15.5.4.1 and
15.5.4.2 show a timing chart and a flowchart, respectively.
Data sending procedure
1.
Set the QSPI_nCTL.DIR bit to 0 when QSPI Ch.n is set to dual or quad transfer mode. (This
setting is not necessary in single transfer mode.)
2.
Assert the slave select signal for the external slave device to be accessed by controlling the
QSPI_nCTL. MSTSSO bit or the general-purpose output port used for an extra slave select signal
output (if necessary).
3.
Check to see if the QSPI_nINTF.TBEIF bit is set to 1 (transmit buffer empty).
4.
Write transmit data to the QSPI_nTXD register.
5.
Wait for a QSPI interrupt when using interrupt.
6.
Repeat Steps 3 to 5 (or 3 and 4) until the end of transmit data.
7.
Negate the slave select signal that has been asserted in Step 2 by controlling the
QSPI_nCTL.MSTSSO bit or the general-purpose output port (if necessary).
Data sending operations
QSPI Ch.n starts data sending operations when transmit data is written into the QSPI_nTXD register.
The transmit data in the QSPI_nTXD register is automatically transferred to the shift register and
the QSPI_ nINTF.TBEIF bit is set to 1. If the QSPI_nINTE.TBEIE bit = 1 (transmit buffer empty
interrupt enabled), a transmit buffer empty interrupt occurs at the same time.
The QSPICLKn pin outputs clocks for the number of cycles specified by the QSPI_nMOD.CHLN[3:0]
bits and the transmit data bits are output in sequence from the QSDIOn pins, according to the transfer
mode specified by the QSPI_nMOD.TMOD[1:0] bits, in sync with these clocks.
Even if the clock is being output from the QSPICLKn pin, the next transmit data can be written to
the QSPI_
nTXD register after making sure the QSPI_nINTF.TBEIF bit is set to 1.
If transmit data has not been written to the QSPI_nTXD register after the last clock is output from
the QSPI- CLKn pin, the clock output halts and the QSPI_nINTF.TENDIF bit is set to 1. At the same
time QSPI issues an end-of-transmission interrupt request if the QSPI_nINTE.TENDIE bit = 1.
QSPICLKn
QSDIOn[3:0]
QSPI_nINTF.TBEIF
QSPI_nINTF.TENDIF
Software operations
Figure 15.5.4.1 Example of Data Sending Operations in Master Mode (QSPI_nMOD.CHDL[3:0] bits =
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
1
1
2
3
4
Data (W) → QSPI_nTXD
Data (W) → QSPI_nTXD
QSPI_nMOD.CHLN[3:0] bits = 0x3)
Seiko Epson Corporation
1
2
3
4
Data (W) → QSPI_nTXD
1 (W) → QSPI_nINTF.TENDIF
2
3
4
15-13
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