Epson S1C31D50 Technical Instructions page 52

CLG IOSC Control Register
Register name Bit
CLGIOSC 15–8
7–5
4
3-2
1–0
Bits 15–5 Reserved
Bit 4 Reserved
Bits 3-2 Reserved
Bits 1–0 IOSCFQ[1:0]
These bits select the IOSCCLK frequency.
IOSCFQ[1:0] bits
2-24
Bit name Initial
– 0x00
– 0x0
– 0
– 0
IOSCFQ[1:0] 0x2
Table 2.6.4 IOSCCLK Frequency Selection
CLGIOSC.
VD1 voltage mode =
mode0
0x3
0x2 8 MHz
0x1 2.0 MHz
0x0 1.0 MHz
Seiko Epson Corporation
Reset R/W
– R
– R
– R
– R
H0 R/WP
IOSCCLK frequency
VD1 voltage mode =
mode1
-
Setting prohibited
1.8 MHz
0.9 MHz
Remarks
–
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)