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WDT2 Counter Compare Match Register
Register name
Bit
WDT2CMP
15–10
9–0
Bits 15–10
Reserved
Bits 9–0
CMP[9:0]
These bits set the NMI/reset generation cycle.
The value set in this register is compared with the 10-bit counter value while WDT2 is
running, and an NMI or reset is generated when they are matched.
9-6
Bit name
Initial
Reset
–
0x00
CMP[9:0]
0x3ff
Seiko Epson Corporation
R/W
–
R
H0
R/WP
S1C31D50 TECHNICAL MANUAL
Remarks
–
(Rev. 1.00)
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