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15.5. Operations
15.5.1. Register Access Mode
Data can be read from or written to the external SPI/QSPI device by accessing the registers in both
master and slave modes.
In single transfer mode, transmit data are always output from the QSDIOn0 pin and receive data are
always input to the QSDIOn1 pin (the QSDIOn[3:2] pins are not used). The operations are backward
compatible with legacy SPI (e.g., synchronous serial interface of this MCU).
In dual transfer mode, transmit data are output from the QSDIOn[1:0] pins when the transfer direction is
set to out- put (QSPI_nCTL.DIR bit = 0). Receive data are input from the QSDIOn[1:0] pins when the
transfer direction is set to input (QSPI_nCTL.DIR bit = 1). The QSDIOn[3:2] pins are not used. The number
of data transfer clocks is con- figured using the QSPI_nMOD.CHLN[3:0] bits. Since two data lines are
used for data transfer, the data bit length (number of clocks) is obtained by dividing the number of
transfer data bits by two.
In quad transfer mode, transmit data are output from the QSDIOn[3:0] pins when the transfer
direction is set to output (QSPI_nCTL.DIR bit = 0). Receive data are input from the QSDIOn[3:0] pins
when the transfer direction is set to input (QSPI_nCTL.DIR bit = 1). The number of data transfer clocks is
configured with the QSPI_nMOD. CHLN[3:0] bits. Since four data lines are used for data transfer, the
data bit length (number of clocks) is obtained by dividing the number of transfer data bits by four.
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Where
LENGTH: Data bit length [clocks]
BIT:
Number of transfer data bits
N:
1 (single transfer mode), 2 (dual transfer mode), or 4 (quad transfer mode)
15.5.2. Memory Mapped Access Mode
Memory mapped access mode is a low CPU overhead operation mode used with master mode to
read data from an external Flash memory, which supports XIP (eXecute-In-Place) mode. Once the
external Flash memory enters XIP mode and a read command is executed, the same read command
operation can be performed by controlling the slave select signal (inactive to active) and sending a new
address to be accessed without the command being resent. This may reduce command re-execution
overhead and random access time.
An XIP session consists of a command cycle, an address cycle, a dummy cycle, and consecutive data
cycles, and it begins with an XIP specific read command similar to a general read command. Unlike a
general read command, one or more data lines must be driven to send XIP activation or termination
confirmation bit(s) at the beginning of the dummy cycle of an XIP session
In an XIP session, to start reading from a non-sequential Flash memory address, which is not continuous
to the previous read address, assert the slave signal again after negating it once. After that, just send an
address cycle to specify the new read start address and a dummy cycle including an XIP activation
(continuation) confirmation bit(s), as the command cycle is not needed in this XIP session. The Flash
memory performs read operations the same as the read command previously executed to execute a
data cycle that includes a given number of data stored from the newly specified address.
To terminate an XIP session, first assert the slave signal again after negating it once. Then, send an
address cycle with the address bits set to all high (suggested by most Flash memory manufacturers) and
a dummy cycle including an XIP termination confirmation bit(s) at the beginning of the cycle on one or
more data lines. After that, negate the slave select signal.
Figures 15.5.2.1 and 15.5.2.2 show Spansion S25FL128S Quad I/O Read command sequences as XIP
operation examples.
15-10
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Seiko Epson Corporation
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S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
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