Epson S1C31D50 Technical Instructions page 216

fifo_read_level
QSPI_nMOD register
#QSPISSn
CPOL bit
CPHA bit
1
1
QSPICLKn
0
0
QSDIOn[3:0]
fifo_read_level
QSPI_nMOD register
#QSPISSn
CPOL bit CPHA bit
1
1
QSPICLKn
0
0
QSDIOn[3:0]
Figure 15.5.6.3 Data Receiving Operation in Memory Mapped Access Mode - 32-bit Non-Sequential Read
Data receiving operations (8/16-bit read)
The 8 and 16-bit read operations are the same as the 32-bit read operation except that data are
not prefetched into the FIFO.
15-22
HCLK
HSEL
HADDR
n
HTRANS
2
HSIZE
2
HREADY
HRDATA
2
#QSPISSn
inactive
period
(TCSH)
HCLK
HSEL
HADDR
HTRANS
HSIZE
HREADY
HRDATA
Address cycle
(low-order 16 bits)
Seiko Epson Corporation
0
Address cycle
(high-order 8/16 bits)
Data cycle
Dummy cycle
(for n)
Address cycle
(low-order 16 bits)
n
1 0
Data cycle
(for n+8))
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)