Epson S1C31D50 Technical Instructions page 103

7.7.3. P2 Port Group
The P2 port group supports the GPIO and interrupt functions.
Register name Bit
PPORTP2DAT 15–8
(P2 Port Data 7–0
Register)
PPORTP2IOEN 15–8
(P2 Port Enable 7–0
Register)
PPORTP2RCTL 15–8
(P2 Port Pull-
7–0
up/down Control
Register)
PPORTP2INTF 15–8
(P2 Port Interrupt 7–0
Flag Register)
PPORTP2INTCTL 15–8
(P2 Port Interrupt
7–0
Control Register)
PPORTP2CHATEN 15–8
(P2 Port Chattering
7–0
Filter Enable
Register)
PPORTP2MODSEL 15–8
(P2 Port Mode
7–0
Select Register)
PPORTP2FNCSEL 15–14
(P2 Port Function
13–12
Select Register)
11–10
9–8
7–6
5–4
3–2
1–0
P2SELy = 0
Port P2yMUX = 0x0
name
GPIO
Peripheral
P20 P20 RFC
P21 P21 RFC
P22 P22 RFC
P23 P23 RFC
P24 P24
P25 P25
P26 P26
P27 P27
*1: Refer to the "Universal Port Multiplexer" chapter.
7-16
Table 7.7.3.1 Control Registers for P2 Port Group
Bit name Initial
P2OUT[7:0] 0x00
P2IN[7:0] 0x00
P2IEN[7:0] 0x00
P2OEN[7:0] 0x00
P2PDPU[7:0] 0x00
P2REN[7:0] 0x00
– 0x00
P2IF[7:0] 0x00
P2EDGE[7:0] 0x00
P2IE[7:0] 0x00
– 0x00
P2CHATEN[7:0] 0x00
– 0x00
P2SEL[7:0] 0x00
P27MUX[1:0] 0x0
P26MUX[1:0] 0x0
P25MUX[1:0] 0x0
P24MUX[1:0] 0x0
P23MUX[1:0] 0x0
P22MUX[1:0] 0x0
P21MUX[1:0] 0x0
P20MUX[1:0] 0x0
Table 7.7.3.2 P2 Port Group Function Assignment
P2yMUX = 0x1
(Function 0) (Function 1)
Pin Peripheral
SENB0 UPMUX
SENA0 UPMUX
REF0 UPMUX
RFIN0 UPMUX
– – UPMUX
– – UPMUX
– – UPMUX
– – UPMUX
Seiko Epson Corporation
Reset R/W
H0 R/W
H0 R
H0 R/W
H0 R/W
H0 R/W
H0 R/W
– R
H0 R/W Cleared by writing 1.
H0 R/W
H0 R/W
– R
H0 R/W
– R
H0 R/W
H0 R/W
H0 R/W
H0 R/W
H0 R/W
H0 R/W
H0 R/W
H0 R/W
H0 R/W
P2SELy = 1
P2yMUX = 0x2
(Function 2)
Pin Peripheral Pin
*1 – –
*1 – –
*1 – –
*1 – –
*1 – –
*1 – –
*1 – –
*1 – –
Remarks
–
–
–
–
–
–
–
–
P2yMUX = 0x3
(Function 3)
Peripheral Pin
– –
– –
– –
– –
– –
– –
– –
– –
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)