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QSPI Ch.n Transmit Data Register
Register name
Bit
QSPI_nTXD
15–0
Bits 15–0
TXD[15:0]
Data can be written to the transmit data buffer through these bits. Writing to these bits
starts data transfer. Transmit data can be written when the QSPI_nINTF.TBEIF bit = 1
regardless of whether data is being output from the QSDIOn pins or not.
Note that the upper data bits that exceed the data bit length configured by the
QSPI_nMOD. CHLN[3:0] bits will not be output from the QSDIOn pin.
Note: Be sure to avoid writing to the QSPI_nTXD register when the QSPI_nINTF.TBEIF
bit = 0. Other- wise, transfer data cannot be guaranteed.
QSPI Ch.n Receive Data Register
Register name
Bit
QSPI_nRXD
15–0
Bits 15–0
RXD[15:0]
The receive data buffer can be read through these bits. Received data can be read when
the QSPI_nINTF.RBFIF bit = 1 regardless of whether data is being input from the QSDIOn
pin or not.
Note that the upper bits that exceed the data bit length configured by the
QSPI_nMOD.CHLN[3:0] bits become 0.
15-36
Bit name
Initial
Reset
TXD[15:0]
0x0000
Bit name
Initial
Reset
RXD[15:0]
0x0000
Seiko Epson Corporation
R/W
H0
R/W
R/W
H0
R
S1C31D50 TECHNICAL MANUAL
Remarks
–
Remarks
–
(Rev. 1.00)
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