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15.6. Interrupts
The QSPI has a function to generate the interrupts shown in Table 15.6.1.
Interrupt
End of transmission
QSPI_nINTF.TENDIF
Receive buffer full
QSPI_nINTF.RBFIF
Transmit buffer
QSPI_nINTF.TBEIF
empty
Overrun error
QSPI_nINTF.OEIF
The QSPI provides interrupt enable bits corresponding to each interrupt flag. An interrupt request is
sent to the CPU core only when the interrupt flag, of which interrupt has been enabled by the
interrupt enable bit, is set. For more information on interrupt control, refer to the "Interrupt" chapter.
The QSPI_nINTF register also contains the BSY and MMABSY bits that indicate the QSPI operating
status in register access and memory mapped access modes, respectively. Figure 15.6.1 shows the
QSPI_nINTF.BSY, QSPI_ nINTF.MMABSY and QSPI_nINTF.TENDIF bit set timings.
15-30
Table 15.6.1 QSPI Interrupt Function
Interrupt flag
When the QSPI_nINTF.TBEIF bit = 1 after
data of the specified bit length (defined by
the QSPI_ nMOD.CHLN[3:0] bits) has been sent
When data of the specified bit length is
received and the received data is transferred
from the shift register to the received data
buffer
When transmit data written to the transmit
data buffer is transferred to the shift register
When the receive data buffer is full (when the
re- ceived data has not been read) at the
point that receiving data to the shift register has
completed
Seiko Epson Corporation
Set condition
S1C31D50 TECHNICAL MANUAL
Clear condition
Writing 1
Reading of the
QSPI_nRXD
register
Writing to the
QSPI_nTXD
register
Writing 1
(Rev. 1.00)
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