Advertisement
DMAC Transfer Completion Interrupt Enable Clear Register
Register name
Bit
DMACENDIECLR
31–0
Bits 31–0
ENDIECLR[31:0]
These bits disable DMA transfer completion interrupts to be generated from each DMAC
channel.
1 (W): Disable interrupt (The DMACENDIESET register is cleared to 0.)
0 (W): Ineffective
Each bit corresponds to a DMAC channel. The high-order bits for the unimplemented
channels are ineffective.
DMAC Error Interrupt Enable Set Register
Register name
Bit
DMACERRIESET
31–24
23–16
15–8
7–1
0
Bits 31–1
Reserved
Bit 0
ERRIESET
This bit enables DMA error interrupts.
1 (W): Enable interrupt
0 (W): Ineffective
1 (R): Interrupt has been enabled.
0 (R): Interrupt has been disabled.
DMAC Error Interrupt Enable Clear Register
Register name
Bit
DMACERRIECLR
31–24
23–16
15–8
7–1
0
Bits 31–1
Reserved
Bit 0
ERRIECLR
This bit disables DMA error interrupts.
1 (W): Disable interrupt (The DMACERRIESET register is cleared to 0.)
0 (W): Ineffective
6-18
Bit name
Initial
ENDIECLR[31:0]
–
Bit name
Initial
–
0x00
–
0x00
–
0x00
–
0x00
ERRIESET
0
Bit name
Initial
–
0x00
–
0x00
–
0x00
–
0x00
ERRIECLR
–
Seiko Epson Corporation
Reset
R/W
–
W
Reset
R/W
–
R
–
R
–
R
–
R
H0
R/W
Reset
R/W
–
R
–
R
–
R
–
R
–
W
Remarks
–
Remarks
–
Remarks
–
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
Advertisement
