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RTCA Interrupt Flag Register
Register name
Bit
RTCAINTF
15
14
13
12
11–9
8
7
6
5
4
3
2
1
0
Bit 15
RTCTRMIF
Bit 14
SW1IF
Bit 13
SW10IF
Bit 12
SW100IF
These bits indicate the real-time clock interrupt cause occurrence status.
1 (R): Cause of interrupt occurred
0 (R): No cause of interrupt occurred
1 (W): Clear flag
0 (W): Ineffective
The following shows the correspondence between the bit and interrupt:
RTCAINTF.RTCTRMIF bit: Theoretical regulation completion interrupt
RTCAINTF.SW1IF bit: Stopwatch 1 Hz interrupt
RTCAINTF.SW10IF bit: Stopwatch 10 Hz interrupt
RTCAINTF.SW100IF bit: Stopwatch 100 Hz interrupt
Bit 11-9
Reserved
Bit 8
ALARMIF
Bit 7
T1DAYIF
Bit 6
T1HURIF
Bit 5
T1MINIF
Bit 4
T1SECIF
Bit 3
T1_2SECIF
Bit 2
T1_4SECIF
Bit 1
T1_8SECIF
Bit 0
T1_32SECIF
These bits indicate the real-time clock interrupt cause occurrence status.
1 (R): Cause of interrupt occurred
0 (R): No cause of interrupt occurred
1 (W): Clear flag
0 (W): Ineffective
The following shows the correspondence between the bit and interrupt:
RTCAINTF. ALARMIF bit:
RTCAINTF.T1DAYIF bit:
RTCAINTF.T1HURIF bit:
RTCAINTF.T1MINIF bit:
RTCAINTF.T1SECIF bit:
RTCAINTF.T1_2SECIF bit:
RTCAINTF.T1_4SECIF bit:
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
Bit name
Initial
RTCTRMIF
0
SW1IF
0
SW10IF
0
SW100IF
0
–
0x0
ALARMIF
0
T1DAYIF
0
T1HURIF
0
T1MINIF
0
T1SECIF
0
T1_2SECIF
0
T1_4SECIF
0
T1_8SECIF
0
T1_32SECIF
0
Alarm interrupt
1-day interrupt
1-hour interrupt
1-minute interrupt
1-second interrupt
1/2-second interrupt
1/4-second interrupt
Seiko Epson Corporation
Reset
R/W
H0
R/W
Cleared by writing 1.
H0
R/W
H0
R/W
H0
R/W
–
R
H0
R/W
Cleared by writing 1.
H0
R/W
H0
R/W
H0
R/W
H0
R/W
H0
R/W
H0
R/W
H0
R/W
H0
R/W
Remarks
–
10-17
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