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Epson S1C31D50 Technical Instructions page 368

Cmos 32-bit single chip microcontroller
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21.5.6. RAM Check March-C Start Command
"RAM Check March-C Start" command can be set under "mc_state_idle" state.
"RAM Check March-C Start" command starts RAM March-C check, the state is moved to
"mc_state_ram_march_c" after the memory check start..
After finishing the memory check, HW Processor makes an interrupt on default and goes to
"mc_state_idle". Please check PROCESSING bit field in STATUS register, it shows OK or ERROR after
check, if ERROR is occurred, please check RESULT register, it shows first fail address.
When state transition is occurred, HW Processor makes an interrupt on default, the interrupt can be
masked by
INTMASK on
Table 21.5.6.1 shows "RAM Check MARCH-C Start" command flow.
Cortex Set HW Processor
Figure 21.5.6.1 "RAM Check March-C Start" Command Flow
21-30
"21.5.11. Memory Check Function Registers".
Wait STATE = "mc_state_idle"
Wait STATUS.READY = mc_status_ready
Set Memory Check COMMAND
-
COMMAND: "RAM Check MARCH-C Start"
-
MEMADDR
- MEMSIZE
in Memory Check Function Registers(See Table 21.5.11.1)
Set HWPCMDTRG.HWP0TRG
Wait HWPINTF.HWP0IF = 1
Check STATE = "mc_state_ram_march_c", if necessary
Wait HWPINTF.HWP0IF = 1
Check STATE = "mc_state_idle"
Check PROCESSING bit field in STATUS register
Check RESULT register if error is occurred
Seiko Epson Corporation
HW Processor interrupts to cortex
HW Processor interrupts to cortex
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)

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