Epson S1C31D50 Technical Instructions page 219

QSPI_nMOD register
CPOL bit
CPHA bit
1
1
0
0
QSDIOn[3:0]
QSPI_ MOD register
n
CPOL bit
CPHA bit
1
1
0 0
QSDIOn[3:0]
Figure 15.5.6.6 Data Receiving Operation in Memory Mapped Access Mode - 8/16-bit Non-Sequential
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
HCLK
HSEL
HADDR
n
HTRANS
2
HSIZE
0/1
HREADY
HRDATA
#QSPISSn
inactive
period
(TCSH)
QSPICLKn
HCLK
HSEL
HADDR
HTRANS
HSIZE
HREADY
HRDATA
Address cycle
(low-order 16 bits)
QSPICLKn
Seiko Epson Corporation
Address cycle
(high-order 8/16 bits)
Dummy cycle
Read
Address cycle
(low-order 16 bits)
n
Data cycle
15-25