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2.3. Clock Generator (CLG)
2.3.1. Overview
CLG is the clock generator that controls the clock sources and manages clock supply to the CPU and
the peripheral circuits. The main features of CLG are outlined below.
•
Supports multiple clock sources.
IOSC oscillator circuit that oscillates with a fast startup and no external parts required
-
Low-power OSC1 oscillator circuit in which the oscillator type can be specified from high-
-
precision 32.768 kHz crystal oscillator (an external resonator is required) and internal oscillator
OSC oscillator circuit can be specified max 16MHz crystal/ceramic oscillator or max 16MHz
-
internal oscillator.
EXOSC clock input circuit that allows input of square wave and sine wave clock signals up to 16
-
MHz
•
The system clock (SYSCLK), which is used as the operating clock for the CPU and bus, and the
peripheral circuit operating clocks can be configured individually by selecting the suitable clock
source and division ratio.
•
Controls the oscillator and clock input circuits to enable/disable according to the operating
mode, RUN or SLEEP mode.
•
Provides a flexible system clock switching function at SLEEP mode cancelation.
The clock sources to be stopped in SLEEP mode can be selected.
-
SYSCLK to be used at SLEEP mode cancelation can be selected from all clock sources.
-
The oscillator and clock input circuit on/off state can be maintained or changed at SLEEP mode
-
cancelation.
•
Provides the FOUT function to output an internal clock for driving external ICs or for
monitoring the internal state.
Figure 2.3.1.1 shows the CLG configuration.
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
Seiko Epson Corporation
2-7
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