Epson S1C17W04 Manuals

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Epson S1C17W04 Technical Manual

Epson S1C17W04 Technical Manual (306 pages)

CMOS 16-BIT SINGLE CHIP MICROCONTROLLER

Brand: Epson | Category: Microcontrollers | Size: 8 MB

Table of Contents

Notational Conventions and Symbols in this Manual
3
Table of Contents
4
Overview
14
Features
14
Block Diagram
16
Pins
17
Pin Configuration Diagram (Package)
17
Pad Configuration Diagram (Chip)
19
Pin Descriptions
20
Power Supply, Reset, and Clocks
23
Power Generator (PWG2)
23
Overview
23
Pins
23
Operations
24
Normal Mode
24
Economy Mode
24
Automatic Mode
24
System Reset Controller (SRC)
26
Overview
26
Input Pin
26
Reset Sources
26
Initialization Conditions (Reset Groups)
27
Clock Generator (CLG)
28
Overview
28
Input/Output Pins
29
Clock Sources
29
Operations
31
System Clock Switching
34
Operating Mode
36
Initial Boot Sequence
36
Transition between Operating Modes
36
Interrupts
38
Control Registers
38
PWG2 Control Register
38
PWG2 Timing Control Register
39
PWG2 Interrupt Flag Register
39
PWG2 Interrupt Enable Register
39
CLG System Clock Control Register
39
CLG Oscillation Control Register
41
CLG IOSC Control Register
41
CLG OSC1 Control Register
42
CLG OSC3 Control Register
43
CLG Interrupt Flag Register
45
CLG Interrupt Enable Register
45
CLG FOUT Control Register
46
CPU and Debugger
48
Overview
48
CPU Core
49
CPU Registers
49
Instruction Set
49
Reading PSR
49
I/O Area Reserved for the S1C17 Core
49
Debugger
49
Debugging Functions
49
Resource Requirements and Debugging Tools
50
List of Debugger Input/Output Pins
50
External Connection
50
Flash Security Function
51
Control Register
51
MISC PSR Register
51
Debug RAM Base Register
52
Memory and Bus
53
Overview
53
Bus Access Cycle
54
Flash Memory
54
Flash Memory Pin
54
Flash Bus Access Cycle Setting
55
Flash Programming
55
Ram
55
Peripheral Circuit Control Registers
55
System-Protect Function
60
Control Registers
60
MISC System Protect Register
60
MISC IRAM Size Register
60
FLASHC Flash Read Cycle Register
60
Interrupt Controller (ITC)
62
Overview
62
Vector Table
62
Vector Table Base Address (TTBR)
64
Initialization
64
Maskable Interrupt Control and Operations
64
Peripheral Circuit Interrupt Control
64
ITC Interrupt Request Processing
65
Conditions to Accept Interrupt Requests by the CPU
65
Nmi
65
Software Interrupts
65
Interrupt Processing by the CPU
66
Control Registers
66
MISC Vector Table Address Low Register
66
MISC Vector Table Address High Register
66
ITC Interrupt Level Setup Register X
66
O Ports (PPORT)
69
Overview
69
I/O Cell Structure and Functions
70
Schmitt Input
70
Over Voltage Tolerant Fail-Safe Type I/O Cell
70
Pull-Up/Pull-Down
70
CMOS Output and High Impedance State
71
Clock Settings
71
PPORT Operating Clock
71
Clock Supply in SLEEP Mode
71
Clock Supply in DEBUG Mode
71
Operations
71
Initialization
71
Port Input/Output Control
73
Interrupts
74
Control Registers
74
Px Port Data Register
74
Px Port Enable Register
75
Px Port Pull-Up/Down Control Register
75
Px Port Interrupt Flag Register
76
Px Port Interrupt Control Register
76
Px Port Chattering Filter Enable Register
76
Px Port Mode Select Register
76
Px Port Function Select Register
77
P Port Clock Control Register
77
P Port Interrupt Flag Group Register
78
Control Register and Port Function Configuration of this IC
79
P0 Port Group
79
P1 Port Group
80
P2 Port Group
81
P3 Port Group
82
P4 Port Group
83
Pd Port Group
84
Common Registers between Port Groups
85
Universal Port Multiplexer (UPMUX)
86
Overview
86
Peripheral Circuit I/O Function Assignment
86
Control Registers
87
Pxy-Xz Universal Port Multiplexer Setting Register
87
Watchdog Timer (WDT)
88
Overview
88
Clock Settings
88
WDT Operating Clock
88
Clock Supply in DEBUG Mode
89
Operations
89
WDT Control
89
Operations in HALT and SLEEP Modes
89
Control Registers
90
WDT Clock Control Register
90
WDT Control Register
90
Real-Time Clock (RTCA)
92
Overview
92
Output Pin and External Connection
92
Output Pin
92
Clock Settings
93
RTCA Operating Clock
93
Theoretical Regulation Function
93
Operations
94
RTCA Control
94
Time Setting
94
Alarm Setting
94
Real-Time Clock Counter Operations
95
Stopwatch Control
95
Stopwatch Count-Up Pattern
95
Interrupts
96
Control Registers
97
RTC Control Register
97
RTC Second Alarm Register
98
RTC Hour/Minute Alarm Register
99
RTC Stopwatch Control Register
99
RTC Second/1Hz Register
100
RTC Hour/Minute Register
101
RTC Month/Day Register
102
RTC Year/Week Register
102
RTC Interrupt Flag Register
103
RTC Interrupt Enable Register
104
Supply Voltage Detector (SVD)
106
Overview
106
Input Pin and External Connection
107
Input Pin
107
External Connection
107
Clock Settings
107
SVD Operating Clock
107
Clock Supply in SLEEP Mode
107
Clock Supply in DEBUG Mode
108
Operations
108
SVD Control
108
SVD Operations
109
SVD Interrupt and Reset
109
SVD Interrupt
109
SVD Reset
110
Control Registers
110
SVD Clock Control Register
110
SVD Control Register
111
SVD Status and Interrupt Flag Register
112
SVD Interrupt Enable Register
113
16-Bit Timers (T16)
114
Overview
114
Input Pin
114
Clock Settings
115
T16 Operating Clock
115
Clock Supply in SLEEP Mode
115
Clock Supply in DEBUG Mode
115
Event Counter Clock
115
Operations
115
Initialization
115
Counter Underflow
116
Operations in Repeat Mode
116
Operations in One-Shot Mode
116
Counter Value Read
117
Interrupt
117
Control Registers
117
T16 Ch.n Clock Control Register
117
T16 Ch.n Mode Register
118
T16 Ch.n Control Register
118
T16 Ch.n Reload Data Register
119
T16 Ch.n Counter Data Register
119
T16 Ch.n Interrupt Flag Register
119
T16 Ch.n Interrupt Enable Register
120
Uart (Uart)
121
Overview
121
Input/Output Pins and External Connections
122
List of Input/Output Pins
122
External Connections
122
Input Pin Pull-Up Function
122
Output Pin Open-Drain Output Function
122
Clock Settings
122
UART Operating Clock
122
Clock Supply in SLEEP Mode
122
Clock Supply in DEBUG Mode
123
Baud Rate Generator
123
Data Format
123
Operations
124
Initialization
124
Data Transmission
124
Data Reception
125
Irda Interface
126
Receive Errors
127
Framing Error
127
Parity Error
128
Overrun Error
128
Interrupts
128
Control Registers
128
UART Ch.n Clock Control Register
128
UART Ch.n Mode Register
129
UART Ch.n Baud-Rate Register
130
UART Ch.n Control Register
130
UART Ch.n Transmit Data Register
131
UART Ch.n Receive Data Register
131
UART Ch.n Status and Interrupt Flag Register
131
UART Ch.n Interrupt Enable Register
132
Synchronous Serial Interface (SPIA)
134
Overview
134
Input/Output Pins and External Connections
135
List of Input/Output Pins
135
External Connections
135
Pin Functions in Master Mode and Slave Mode
136
Input Pin Pull-Up/Pull-Down Function
136
Clock Settings
136
SPIA Operating Clock
136
Clock Supply in DEBUG Mode
137
SPI Clock (Spiclkn) Phase and Polarity
137
Data Format
138
Operations
138
Initialization
138
Data Transmission in Master Mode
138
Data Reception in Master Mode
140
Terminating Data Transfer in Master Mode
141
Data Transfer in Slave Mode
141
Data Sending Procedure
141
Terminating Data Transfer in Slave Mode
143
Interrupts
143
Control Registers
144
SPIA Ch.n Mode Register
144
SPIA Ch.n Control Register
145
SPIA Ch.n Transmit Data Register
146
SPIA Ch.n Receive Data Register
146
SPIA Ch.n Interrupt Flag Register
146
SPIA Ch.n Interrupt Enable Register
147
C (I2C)
148
Overview
148
Input/Output Pins and External Connections
149
List of Input/Output Pins
149
External Connections
149
Clock Settings
150
I2C Operating Clock
150
Clock Supply in DEBUG Mode
150
Baud Rate Generator
150
Operations
151
Initialization
151
Data Transmission in Master Mode
152
Data Reception in Master Mode
154
Data Receiving Procedure
154
10-Bit Addressing in Master Mode
156
Data Transmission in Slave Mode
157
Data Reception in Slave Mode
159
Slave Operations in 10-Bit Address Mode
161
Automatic Bus Clearing Operation
161
Error Detection
162
Interrupts
163
Control Registers
164
I2C Ch.n Clock Control Register
164
I2C Ch.n Mode Register
165
I2C Ch.n Baud-Rate Register
165
I2C Ch.n Own Address Register
165
I2C Ch.n Control Register
166
I2C Ch.n Transmit Data Register
167
I2C Ch.n Receive Data Register
167
I2C Ch.n Status and Interrupt Flag Register
167
I2C Ch.n Interrupt Enable Register
168
16-Bit PWM Timers (T16B)
170
Overview
170
Input/Output Pins
171
Clock Settings
172
T16B Operating Clock
172
Clock Supply in SLEEP Mode
172
Clock Supply in DEBUG Mode
172
Event Counter Clock
172
Operations
173
Initialization
173
Counter Block Operations
174
Comparator/Capture Block Operations
177
TOUT Output Control
185
Interrupt
191
Control Registers
191
T16B Ch.n Clock Control Register
191
T16B Ch.n Counter Control Register
192
T16B Ch.n Max Counter Data Register
193
T16B Ch.n Timer Counter Data Register
193
T16B Ch.n Counter Status Register
194
T16B Ch.n Interrupt Flag Register
195
T16B Ch.n Interrupt Enable Register
196
T16B Ch.n Comparator/Capture M Control Register
197
T16B Ch.n Compare/Capture M Data Register
199
Sound Generator (SNDA)
200
Overview
200
Output Pins and External Connections
201
List of Output Pins
201
Output Pin Drive Mode
201
External Connections
201
Clock Settings
202
SNDA Operating Clock
202
Clock Supply in SLEEP Mode
202
Clock Supply in DEBUG Mode
202
Operations
202
Initialization
202
Buzzer Output in Normal Buzzer Mode
202
Buzzer Output in One-Shot Buzzer Mode
205
Output in Melody Mode
206
Interrupts
208
Control Registers
208
SNDA Clock Control Register
208
SNDA Select Register
209
SNDA Control Register
210
SNDA Data Register
210
SNDA Interrupt Flag Register
211
SNDA Interrupt Enable Register
212
IR Remote Controller (REMC2)
213
Overview
213
Input/Output Pins and External Connections
213
Output Pin
213
External Connections
214
Clock Settings
214
REMC2 Operating Clock
214
Clock Supply in SLEEP Mode
214
Clock Supply in DEBUG Mode
214
Operations
214
Initialization
214
Data Transmission Procedures
215
REMO Output Waveform
215
Continuous Data Transmission and Compare Buffers
217
Interrupts
218
Application Example: Driving el Lamp
219
Control Registers
219
REMC2 Clock Control Register
219
REMC2 Data Bit Counter Control Register
220
REMC2 Data Bit Counter Register
221
REMC2 Data Bit Active Pulse Length Register
222
REMC2 Data Bit Length Register
222
REMC2 Status and Interrupt Flag Register
222
REMC2 Interrupt Enable Register
223
REMC2 Carrier Waveform Register
223
REMC2 Carrier Modulation Control Register
224
F Converter (RFC)
225
Overview
225
Input/Output Pins and External Connections
226
List of Input/Output Pins
226
External Connections
226
Clock Settings
227
RFC Operating Clock
227
Clock Supply in SLEEP Mode
227
Clock Supply in DEBUG Mode
227
Operations
227
Initialization
227
Operating Modes
228
Oscillation Mode
228
RFC Counters
228
Converting Operations and Control Procedure
229
Forced Termination
230
CR Oscillation Frequency Monitoring Function
231
Interrupts
231
Control Registers
232
RFC Ch.n Clock Control Register
232
RFC Ch.n Control Register
232
RFC Ch.n Oscillation Trigger Register
233
RFC Ch.n Measurement Counter Low and High Registers
234
RFC Ch.n Time Base Counter Low and High Registers
234
RFC Ch.n Interrupt Flag Register
235
RFC Ch.n Interrupt Enable Register
235
12-Bit A/D Converter (ADC12A)
236
Overview
236
Input Pins and External Connections
237
List of Input Pins
237
External Connections
237
Clock Settings
237
ADC12A Operating Clock
237
Sampling Time
237
Operations
238
Initialization
238
Conversion Start Trigger Source
238
Conversion Mode and Analog Input Pin Settings
239
A/D Conversion Operations and Control Procedures
239
Interrupts
241
Control Registers
241
ADC12A Ch.n Control Register
241
ADC12A Ch.n Trigger/Analog Input Select Register
242
ADC12A Ch.n Configuration Register
243
ADC12A Ch.n Interrupt Flag Register
244
ADC12A Ch.n Interrupt Enable Register
245
ADC12A Ch.n Result Register M
245
Multiplier/Divider (COPRO2)
246
Overview
246
Operation Mode and Output Mode
246
Multiplication
247
Division
248
Mac
250
Reading Operation Results
252
Electrical Characteristics
253
Absolute Maximum Ratings
253
Recommended Operating Conditions
253
Current Consumption
254
System Reset Controller (SRC) Characteristics
256
Clock Generator (CLG) Characteristics
256
Flash Memory Characteristics
259
Input/Output Port (PPORT) Characteristics
259
Supply Voltage Detector (SVD) Characteristics
260
UART (UART) Characteristics
261
Synchronous Serial Interface (SPIA) Characteristics
262
I 2 C (I2C) Characteristics
263
R/F Converter (RFC) Characteristics
263
12-Bit A/D Converter (ADC12A) Characteristics
264
Basic External Connection Diagram
266
Package
268
Appendix A List of Peripheral Circuit Control Registers
270
0X41B0 Flash Controller (FLASHC)
276
0X4200-0X42E2 I/O Ports (PPORT)
276
0X43C0-0X43D2 I
283
C (I2C)
283
Debugger (DBG)
294
Appendix B Power Saving
295
Operating Status Configuration Examples for Power Saving
295
Other Power Saving Methods
296
Appendix C Mounting Precautions
297
Power Supply Circuit
297
Unused Pins
298
Appendix D Measures against Noise
300

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Epson S1C17W04 Technical Manual

Epson S1C17W04 Technical Manual (307 pages)

CMOS 16-BIT SINGLE CHIP MICROCONTROLLER

Brand: Epson | Category: Microcontrollers | Size: 8 MB

Table of Contents

Notational Conventions and Symbols in this Manual
3
Table of Contents
4
Overview
14
Features
14
Block Diagram
16
Pins
17
Pin Configuration Diagram (Package)
17
Pad Configuration Diagram (Chip)
19
Pin Descriptions
20
Power Supply, Reset, and Clocks
23
Power Generator (PWG2)
23
Overview
23
Pins
23
Operations
24
System Reset Controller (SRC)
26
Overview
26
Input Pin
26
Reset Sources
26
Initialization Conditions (Reset Groups)
27
Clock Generator (CLG)
28
Overview
28
Input/Output Pins
29
Clock Sources
29
Operations
31
Operating Mode
36
Initial Boot Sequence
36
Transition between Operating Modes
36
Interrupts
38
Control Registers
38
PWG2 Control Register
38
PWG2 Timing Control Register
39
PWG2 Interrupt Flag Register
39
PWG2 Interrupt Enable Register
39
CLG System Clock Control Register
39
CLG Oscillation Control Register
41
CLG IOSC Control Register
41
CLG OSC1 Control Register
42
CLG OSC3 Control Register
43
CLG Interrupt Flag Register
45
CLG Interrupt Enable Register
45
CLG FOUT Control Register
46
CPU and Debugger
48
Overview
48
CPU Core
49
CPU Registers
49
Instruction Set
49
Reading PSR
49
I/O Area Reserved for the S1C17 Core
49
Debugger
49
Debugging Functions
49
Resource Requirements and Debugging Tools
50
List of Debugger Input/Output Pins
50
External Connection
50
Flash Security Function
51
Control Register
51
MISC PSR Register
51
Debug RAM Base Register
52
Memory and Bus
53
Overview
53
Bus Access Cycle
54
Flash Memory
54
Flash Memory Pin
54
Flash Bus Access Cycle Setting
55
Flash Programming
55
Ram
55
Peripheral Circuit Control Registers
55
System-Protect Function
60
Control Registers
60
MISC System Protect Register
60
MISC IRAM Size Register
60
FLASHC Flash Read Cycle Register
60
Interrupt Controller (ITC)
62
Overview
62
Vector Table
62
Vector Table Base Address (TTBR)
64
Initialization
64
Maskable Interrupt Control and Operations
64
Peripheral Circuit Interrupt Control
64
ITC Interrupt Request Processing
65
Conditions to Accept Interrupt Requests by the CPU
65
Nmi
65
Software Interrupts
65
Interrupt Processing by the CPU
66
Control Registers
66
MISC Vector Table Address Low Register
66
MISC Vector Table Address High Register
66
ITC Interrupt Level Setup Register X
66
O Ports (PPORT)
69
Overview
69
I/O Cell Structure and Functions
70
Schmitt Input
70
Over Voltage Tolerant Fail-Safe Type I/O Cell
70
Pull-Up/Pull-Down
70
CMOS Output and High Impedance State
71
Clock Settings
71
PPORT Operating Clock
71
Clock Supply in SLEEP Mode
71
Clock Supply in DEBUG Mode
71
Operations
71
Initialization
71
Port Input/Output Control
73
Interrupts
74
Control Registers
74
Px Port Data Register
74
Px Port Enable Register
75
Px Port Pull-Up/Down Control Register
75
Px Port Interrupt Flag Register
76
Px Port Interrupt Control Register
76
Px Port Chattering Filter Enable Register
76
Px Port Mode Select Register
76
Px Port Function Select Register
77
P Port Clock Control Register
77
P Port Interrupt Flag Group Register
78
Control Register and Port Function Configuration of this IC
79
P0 Port Group
79
P1 Port Group
80
P2 Port Group
81
P3 Port Group
82
P4 Port Group
83
Pd Port Group
84
Common Registers between Port Groups
85
Universal Port Multiplexer (UPMUX)
86
Overview
86
Peripheral Circuit I/O Function Assignment
86
Control Registers
87
Pxy-Xz Universal Port Multiplexer Setting Register
87
Watchdog Timer (WDT)
88
Overview
88
Clock Settings
88
WDT Operating Clock
88
Clock Supply in DEBUG Mode
89
Operations
89
WDT Control
89
Operations in HALT and SLEEP Modes
89
Control Registers
90
WDT Clock Control Register
90
WDT Control Register
90
Real-Time Clock (RTCA)
92
Overview
92
Output Pin and External Connection
92
Output Pin
92
Clock Settings
93
RTCA Operating Clock
93
Theoretical Regulation Function
93
Operations
94
RTCA Control
94
Real-Time Clock Counter Operations
95
Stopwatch Control
95
Stopwatch Count-Up Pattern
95
Interrupts
96
Control Registers
97
RTC Control Register
97
RTC Second Alarm Register
98
RTC Hour/Minute Alarm Register
99
RTC Stopwatch Control Register
99
RTC Second/1Hz Register
100
RTC Hour/Minute Register
101
RTC Month/Day Register
102
RTC Year/Week Register
102
RTC Interrupt Flag Register
103
RTC Interrupt Enable Register
104
Supply Voltage Detector (SVD)
106
Overview
106
Input Pin and External Connection
107
Input Pin
107
External Connection
107
Clock Settings
107
SVD Operating Clock
107
Clock Supply in SLEEP Mode
107
Clock Supply in DEBUG Mode
108
Operations
108
SVD Control
108
SVD Operations
109
SVD Interrupt and Reset
109
SVD Interrupt
109
SVD Reset
110
Control Registers
110
SVD Clock Control Register
110
SVD Control Register
111
SVD Status and Interrupt Flag Register
112
SVD Interrupt Enable Register
113
16-Bit Timers (T16)
114
Overview
114
Input Pin
114
Clock Settings
115
T16 Operating Clock
115
Clock Supply in SLEEP Mode
115
Clock Supply in DEBUG Mode
115
Event Counter Clock
115
Operations
115
Initialization
115
Counter Underflow
116
Operations in Repeat Mode
116
Operations in One-Shot Mode
116
Counter Value Read
117
Interrupt
117
Control Registers
117
T16 Ch.n Clock Control Register
117
T16 Ch.n Mode Register
118
T16 Ch.n Control Register
118
T16 Ch.n Reload Data Register
119
T16 Ch.n Counter Data Register
119
T16 Ch.n Interrupt Flag Register
119
T16 Ch.n Interrupt Enable Register
120
Uart (Uart)
121
Overview
121
Input/Output Pins and External Connections
122
List of Input/Output Pins
122
External Connections
122
Input Pin Pull-Up Function
122
Output Pin Open-Drain Output Function
122
Clock Settings
122
UART Operating Clock
122
Clock Supply in SLEEP Mode
122
Clock Supply in DEBUG Mode
123
Baud Rate Generator
123
Data Format
123
Operations
124
Initialization
124
Data Transmission
124
Data Reception
125
Irda Interface
126
Receive Errors
127
Framing Error
127
Parity Error
128
Overrun Error
128
Interrupts
128
Control Registers
128
UART Ch.n Clock Control Register
128
UART Ch.n Mode Register
129
UART Ch.n Baud-Rate Register
130
UART Ch.n Control Register
130
UART Ch.n Transmit Data Register
131
UART Ch.n Receive Data Register
131
UART Ch.n Status and Interrupt Flag Register
131
Synchronous Serial Interface (SPIA)
134
Overview
134
Input/Output Pins and External Connections
135
List of Input/Output Pins
135
External Connections
135
Pin Functions in Master Mode and Slave Mode
136
Input Pin Pull-Up/Pull-Down Function
136
Clock Settings
136
SPIA Operating Clock
136
Clock Supply in DEBUG Mode
137
SPI Clock (Spiclkn) Phase and Polarity
137
Data Format
138
Operations
138
Initialization
138
Data Transmission in Master Mode
138
Data Reception in Master Mode
140
Terminating Data Transfer in Master Mode
141
Data Transfer in Slave Mode
141
Terminating Data Transfer in Slave Mode
143
Interrupts
143
Control Registers
144
SPIA Ch.n Mode Register
144
SPIA Ch.n Control Register
145
SPIA Ch.n Transmit Data Register
146
SPIA Ch.n Receive Data Register
146
SPIA Ch.n Interrupt Flag Register
146
SPIA Ch.n Interrupt Enable Register
147
C (I2C)
148
Overview
148
Input/Output Pins and External Connections
149
List of Input/Output Pins
149
External Connections
149
Clock Settings
150
I2C Operating Clock
150
Clock Supply in DEBUG Mode
150
Baud Rate Generator
150
Operations
151
Initialization
151
Data Transmission in Master Mode
152
Data Reception in Master Mode
154
10-Bit Addressing in Master Mode
156
Data Transmission in Slave Mode
157
Data Reception in Slave Mode
159
Slave Operations in 10-Bit Address Mode
161
Automatic Bus Clearing Operation
161
Error Detection
162
Interrupts
163
Control Registers
164
I2C Ch.n Clock Control Register
164
I2C Ch.n Mode Register
165
I2C Ch.n Baud-Rate Register
165
I2C Ch.n Own Address Register
165
I2C Ch.n Control Register
166
I2C Ch.n Transmit Data Register
167
I2C Ch.n Receive Data Register
167
I2C Ch.n Status and Interrupt Flag Register
167
I2C Ch.n Interrupt Enable Register
168
16-Bit PWM Timers (T16B)
170
Overview
170
Input/Output Pins
171
Clock Settings
172
T16B Operating Clock
172
Clock Supply in SLEEP Mode
172
Clock Supply in DEBUG Mode
172
Event Counter Clock
172
Operations
173
Initialization
173
Counter Block Operations
174
Comparator/Capture Block Operations
177
TOUT Output Control
185
Interrupt
191
Control Registers
191
T16B Ch.n Clock Control Register
191
T16B Ch.n Counter Control Register
192
T16B Ch.n Max Counter Data Register
193
T16B Ch.n Timer Counter Data Register
193
T16B Ch.n Counter Status Register
194
T16B Ch.n Interrupt Flag Register
195
T16B Ch.n Interrupt Enable Register
196
T16B Ch.n Comparator/Capture M Control Register
197
T16B Ch.n Compare/Capture M Data Register
199
Sound Generator (SNDA)
200
Overview
200
Output Pins and External Connections
201
List of Output Pins
201
Output Pin Drive Mode
201
External Connections
201
Clock Settings
202
SNDA Operating Clock
202
Clock Supply in SLEEP Mode
202
Clock Supply in DEBUG Mode
202
Operations
202
Initialization
202
Buzzer Output in Normal Buzzer Mode
202
Buzzer Output in One-Shot Buzzer Mode
205
Output in Melody Mode
206
Interrupts
208
Control Registers
208
SNDA Clock Control Register
208
SNDA Select Register
209
SNDA Control Register
210
SNDA Data Register
210
SNDA Interrupt Flag Register
211
SNDA Interrupt Enable Register
212
IR Remote Controller (REMC2)
213
Overview
213
Input/Output Pins and External Connections
213
Output Pin
213
External Connections
214
Clock Settings
214
REMC2 Operating Clock
214
Clock Supply in SLEEP Mode
214
Clock Supply in DEBUG Mode
214
Operations
214
Initialization
214
Data Transmission Procedures
215
REMO Output Waveform
215
Continuous Data Transmission and Compare Buffers
217
Interrupts
218
Application Example: Driving el Lamp
219
Control Registers
219
REMC2 Clock Control Register
219
REMC2 Data Bit Counter Control Register
220
REMC2 Data Bit Counter Register
221
REMC2 Data Bit Active Pulse Length Register
222
REMC2 Data Bit Length Register
222
REMC2 Status and Interrupt Flag Register
222
REMC2 Interrupt Enable Register
223
REMC2 Carrier Waveform Register
223
REMC2 Carrier Modulation Control Register
224
F Converter (RFC)
225
Overview
225
Input/Output Pins and External Connections
226
List of Input/Output Pins
226
External Connections
226
Clock Settings
227
RFC Operating Clock
227
Clock Supply in SLEEP Mode
227
Clock Supply in DEBUG Mode
227
Operations
227
Initialization
227
Operating Modes
228
RFC Counters
228
Converting Operations and Control Procedure
229
CR Oscillation Frequency Monitoring Function
231
Interrupts
231
Control Registers
232
RFC Ch.n Clock Control Register
232
RFC Ch.n Control Register
232
RFC Ch.n Oscillation Trigger Register
233
RFC Ch.n Measurement Counter Low and High Registers
234
RFC Ch.n Time Base Counter Low and High Registers
234
RFC Ch.n Interrupt Flag Register
235
RFC Ch.n Interrupt Enable Register
235
12-Bit A/D Converter (ADC12A)
236
Overview
236
Input Pins and External Connections
237
List of Input Pins
237
External Connections
237
Clock Settings
237
ADC12A Operating Clock
237
Sampling Time
237
Operations
238
Initialization
238
Conversion Start Trigger Source
238
Conversion Mode and Analog Input Pin Settings
239
A/D Conversion Operations and Control Procedures
239
Interrupts
241
Control Registers
241
ADC12A Ch.n Control Register
241
ADC12A Ch.n Trigger/Analog Input Select Register
242
ADC12A Ch.n Configuration Register
243
ADC12A Ch.n Interrupt Flag Register
244
ADC12A Ch.n Interrupt Enable Register
245
ADC12A Ch.n Result Register M
245
Multiplier/Divider (COPRO2)
246
Overview
246
Operation Mode and Output Mode
246
Multiplication
247
Division
248
Mac
250
Reading Operation Results
252
Electrical Characteristics
253
Absolute Maximum Ratings
253
Recommended Operating Conditions
253
Current Consumption
254
System Reset Controller (SRC) Characteristics
256
Clock Generator (CLG) Characteristics
256
Flash Memory Characteristics
259
Input/Output Port (PPORT) Characteristics
259
Supply Voltage Detector (SVD) Characteristics
260
UART (UART) Characteristics
261
Synchronous Serial Interface (SPIA) Characteristics
262
I 2 C (I2C) Characteristics
263
R/F Converter (RFC) Characteristics
263
12-Bit A/D Converter (ADC12A) Characteristics
264
Basic External Connection Diagram
266
Package
268
Appendix A List of Peripheral Circuit Control Registers
270
0X41B0 Flash Controller (FLASHC)
276
0X4200-0X42E2 I/O Ports (PPORT)
276
0X43C0-0X43D2 I
283
C (I2C)
283
Appendix B Power Saving
295
Operating Status Configuration Examples for Power Saving
295
Other Power Saving Methods
296
Appendix C Mounting Precautions
297
Appendix D Measures against Noise
300

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