Advertisement
15.2.3. Pin Functions in Master Mode and Slave Mode
The pin functions are changed according to the transfer direction, transfer mode, and master/slave
mode selections. The differences in pin functions between the modes are shown in Table 15.2.3.1.
Pin
Single transfer mode Dual transfer
QSDIOn[3:2] Always placed into Hi-Z state.
Always
placed
QSDIOn1
into input state.
Always
placed
QSDIOn0
into output state.
Outputs the QSPI clock to external devices.
QSPICLKn
Output clock polarity and phase can be configured if nec-
essary.
This pin is used to output the slave select signal in mas-
#QSPISSn
ter mode. In memory mapped access mode, this pin is
controlled by the internal state machine. In register ac-
cess mode, this pin is controlled by a register bit. When
connecting more than one external slave device, general-
purpose I/O ports can be used to output the extra slave
select signals.
15.2.4. Input Pin Pull-Up/Pull-Down Function
The QSPI pins (QSDIOn[3:0] pins in master mode or QSDIOn[3:0] pins, QSPICLKn, and #QSPISSn pins in
slave mode) have a pull-up or pull-down function as shown in Table 15.2.4.1. This function is enabled
by setting the QSPI_nMOD.PUEN bit to 1.
Pin
QSDIOn[3:0]
QSPICLKn
#QSPISSn
15-6
Table 15.2.3.1 Pin Function Differences between Modes
Function in master mode
Quad transfer
mode
mode
T h e s e p i n s a r e
placed
T h e s e p i n s a r e
input o r o u t p u t
placed
into
s t a t e according
input o r o u t p u t
to
s t a t e according
QSPI_nCTL.DIR bit
to
the
setting.
QSPI_nCTL.DIR bit
setting.
Table 15.2.4.1 Pull-Up or Pull-Down of QSPI Pins
Master mode
Pull-up
–
–
Seiko Epson Corporation
Function in slave mode
Single transfer mode Dual transfer
mode
Always placed into Hi-Z state.
into
Always
placed
T h e s e p i n s a r e
into input state.
placed
output
This pin is placed
the
while
into output state
l e v e l i s a p p l i e d
while
a
low
to the #QSPISSn
level is applied
to the
pin and the QSPI_
#QSPISSn pin or
nCTL.DIR bit is set
placed into Hi-Z
to 0 (ou tp ut) ,
state
while
a
or placed into
Hi-Z state while
high
level
is
a high level is
applied
to
the
applied
#QSPISSn pin.
#QSPISSn pin or
the
DIR bit is set to 1
(input).
Inputs an external QSPI clock.
Clock polarity and phase can be designated according to
the input clock.
Applying a low level to the #QSPISSn pin enables the
QSPI to transmit/receive data. While a high level is applied
to this pin, the QSPI is not selected as a slave device. Data
input to the QSDIOn pins and the clock input to the QSPI-
CLKn pin are ignored. When a high level is applied, the
transmit/receive bit count is cleared to 0 and the already
received bits are discarded.
Slave mode
Pull-up
QSPI_nMOD.CPOL bit = 1: Pull-up
QSPI_nMOD.CPOL bit = 0: Pull-down
Pull-up
Quad transfer
mode
T h e s e p i n s a r e
placed
into
output
state
into
while
a
low
state
l e v e l i s a p p l i e d
a
low
to the #QSPISSn
pin and the QSPI_
nCTL.DIR bit is set
to 0 (o ut put) ,
or placed
into
Hi-Z state while
a high level is
applied
to
the
#QSPISSn pin or
to
the
the
QSPI_nCTL.
DIR bit is set to 1
QSPI_nCTL.
(input).
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
Advertisement
