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Bit 6
CNVMD
Figure 19.7.1 Conversion Data Alignment
This bit sets the A/D conversion mode.
1 (R/W): Continuous conversion mode
0 (R/W): One-time conversion mode
Bits 5–4
CNVTRG[1:0]
These bits select a trigger source to start A/D conversion.
ADC12A_nTRG.CNVTRG[1:0] bits
Bit 3
Reserved
Bits 2–0
SMPCLK[2:0]
These bits set the analog input signal sampling time.
ADC12A_nTRG.SMPCLK[2:0] bits
19-10
Table 19.7.2 Trigger Source Selection
0x3
0x2
0x1
0x0
ADC12A_nCTL.ADST bit (software trigger)
Table 19.7.3 Sampling Time Settings
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
Seiko Epson Corporation
Trigger source
#ADTRGn pin (external trigger)
Reserved
16-bit timer Ch.k underflow
Sampling time
(Number of CLK_T16_k cycles)
11 cycles
10 cycles
9 cycles
8 cycles
7 cycles
6 cycles
5 cycles
4 cycles
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
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