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Epson S1C17 Series Manual

Cmos 16-bit single chip microcontroller.
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CMOS 16-BIT SINGLE CHIP MICROCONTROLLER
S1C17 Family
S1C17 Core Manual
Rev. 1.2

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Table of Contents

   Related Manuals for Epson S1C17 Series

   Summary of Contents for Epson S1C17 Series

  • Page 1 CMOS 16-BIT SINGLE CHIP MICROCONTROLLER S1C17 Family S1C17 Core Manual Rev. 1.2...
  • Page 2 No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability...
  • Page 3: Table Of Contents

    5.2.3 Register Indirect Addressing ................5-6 5.2.4 Register Indirect Addressing with Post-increment/decrement or Pre-decrement ... 5-6 5.2.5 Register Indirect Addressing with Displacement..........5-7 5.2.6 Signed PC Relative Addressing ................5-7 5.2.7 PC Absolute Addressing ..................5-7 Seiko Epson Corporation S1C17 CORE MANUAL (Rev. 1.2)
  • Page 4 %rd, %rs ..........................7-3 %rd, imm7 .......................... 7-4 %rd, %rs ..........................7-5 add/c %rd, %rs ..........................7-5 add/nc %rd, %rs ..........................7-5 %rd, imm7 .......................... 7-6 add.a %rd, %rs ..........................7-7 Seiko Epson Corporation S1C17 CORE MANUAL (REV. 1.2)
  • Page 5 ..........................7-42 jrge sign7 ..........................7-43 jrge.d sign7 ..........................7-43 jrgt sign7 ..........................7-44 jrgt.d sign7 ..........................7-44 jrle sign7 ..........................7-45 jrle.d sign7 ..........................7-45 jrlt sign7 ..........................7-46 Seiko Epson Corporation S1C17 CORE MANUAL (Rev. 1.2)
  • Page 6 %rd, [%rb] ......................... 7-87 ld.b %rd, [%rb]+ ........................7-88 ld.b %rd, [%rb]- ........................7-88 ld.b %rd, -[%rb] ........................7-88 ld.b %rd, [%sp + imm7] ......................7-90 ld.b %rd, [imm7] ........................7-91 ld.b [%rb], %rs.......................... 7-92 Seiko Epson Corporation S1C17 CORE MANUAL (REV. 1.2)
  • Page 7 %sp, %rs .......................... 7-130 sub.a %sp, imm7 ........................7-131 swap %rd, %rs ........................... 7-132 %rd, %rs ........................... 7-133 xor/c %rd, %rs ........................... 7-133 xor/nc %rd, %rs ........................... 7-133 %rd, sign7 ........................7-134 Seiko Epson Corporation S1C17 CORE MANUAL (Rev. 1.2)
  • Page 8 CONTENTS Appendix List of S1C17 Core Instructions ..............Ap-1 Revision History Seiko Epson Corporation S1C17 CORE MANUAL (REV. 1.2)
  • Page 9: Features

    The S1C17 Core incorporates a coprocessor interface allowing implementation of additional computing features. Furthermore, Seiko Epson provides a software development environment similar to the S1C33 Family that includes an IDE work bench, a C compiler, a serial ICE and a debugger, for supporting the developer to develop application software.
  • Page 10: Registers

    At an initial reset, the reset vector (address) written at the top of vector table indicated by TTBR is loaded into the PC, and the processor starts executing a program from the address indicated by the PC. Effective address Figure 2.2.1 Program Counter (PC) Seiko Epson Corporation S1C17 CORE MANUAL (Rev. 1.2)
  • Page 11: Processor Status Register (psr)

    (6) When a shift operation of the register in which bit 15 is 1 is executed using a left logical shift instruction (7) When a shift operation of the register in which bit 0 is 1 is executed using a right arithmetic shift instruction Seiko Epson Corporation S1C17 CORE MANUAL...
  • Page 12 This bit indicates a sign. More specifically, the most significant bit (bit 15) of the result of a logical operation, arithmetic operation, or shift instruction is copied to this N flag. Note that 16-bit arithmetic operation instructions can set the N flag, but 24-bit arithmetic operation instructions cannot. Seiko Epson Corporation S1C17 CORE MANUAL (Rev. 1.2)
  • Page 13: Stack Pointer (sp)

    SP operation by the call/calla instruction (1) SP = SP - 4 (2) PC + 2 → [SP] 0xffffff 0xffffff 0x00 PC[23:16] PC[15:8] SP = SP - 4 PC[7:0] 0x000000 0x000000 Figure 2.4.2.1 SP and Stack (1) Seiko Epson Corporation S1C17 CORE MANUAL (REV. 1.2)
  • Page 14: Sp Operation When An Interrupt Occurs

    (2) [SP+ 3] → PSR (3) SP = SP + 4 0xffffff 0xffffff SP = SP + 4 PC[23:16] PC[23:16] PC[15:8] PC[15:8] PC[7:0] PC[7:0] 0x000000 0x000000 Figure 2.4.3.2 SP and Stack (4) Seiko Epson Corporation S1C17 CORE MANUAL (Rev. 1.2)
  • Page 15: Saving/restoring Register Data Using A Load Instruction

    Figure 2.4.4.2 SP and Stack (6) In addition to the instructions shown above, some other load instructions have been provided for operating the stack. Refer to Chapter 7, “Details of Instructions,” for more information on those instructions. Seiko Epson Corporation S1C17 CORE MANUAL (REV. 1.2)
  • Page 16: Register Notation And Register Numbers

    The special registers that can be directly specified in the S1C17 Core instructions are the SP (Stack Pointer) and PC (Program Counter) only. The register is actually written as %sp, [%sp], -[%sp], [%sp]+, [%sp]-, [%sp+imm7], or %pc. Seiko Epson Corporation S1C17 CORE MANUAL (Rev. 1.2)
  • Page 17: Data Formats

    3.1.2 Signed 8-Bit Transfer (Register → Register) Example: ld.b %rd,%rs Byte 16 15 Byte Figure 3.1.2.1 Signed 8-Bit Transfer (Register → Register) Bits 15–8 in the destination register are sign-extended and bits 23–16 are set to 0x00. Seiko Epson Corporation S1C17 CORE MANUAL (Rev. 1.2)
  • Page 18: 16-bit Transfer (register → Register)

    However, the eight high-order bits are effective as the PSR value only in the stack operation when an interrupt occurs. The data transfer sizes and types are described below. Seiko Epson Corporation S1C17 CORE MANUAL (REV. 1.2)
  • Page 19: Unsigned 8-bit Transfer (memory → Register)

    Example: ld %rd,[%rb] 0b*****1 Byte 1 [%rb] 0b*****0 Byte 0 16 15 Byte 1 Byte 0 Figure 3.2.4.1 16-Bit Transfer (Memory → Register) Bits 23–16 in the destination register are set to 0x00. Seiko Epson Corporation S1C17 CORE MANUAL (Rev. 1.2)
  • Page 20: 16-bit Transfer (register → Memory)

    3.2.7 32-Bit Transfer (Register → Memory) Example: ld.a [%rb],%rs 16 15 Byte 2 Byte 1 Byte 0 0b******11 0x00 0b******10 Byte 2 0b******01 Byte 1 [%rb] 0b******00 Byte 0 Figure 3.2.7.1 32-Bit Transfer (Register → Memory) Seiko Epson Corporation S1C17 CORE MANUAL (REV. 1.2)
  • Page 21: Address Map

    0xff fbff 0x00 0000 Figure 4.1.1 Address Space of the S1C17 Core The boot address and debug RAM address depend on the specifications of each the S1C17 Series models. Refer to the Technical Manual of each model. Seiko Epson Corporation S1C17 CORE MANUAL (Rev.
  • Page 22: Processor Information In The Core I/o Area

    Refer to the Technical Manual of each model for the address stored in this register. * In addition to the above registers, the reserved core I/O area contains some registers for debugging. For the debug registers, refer to Section 6.5, “Debug Circuit.” Seiko Epson Corporation S1C17 CORE MANUAL (REV. 1.2)
  • Page 23: Instruction Set

    [imm7],%rs SP → general-purpose register %rd,%sp PC → general-purpose register %rd,%pc Stack (32 bits) → general-purpose register * %rd,[%sp] Stack pointer post-increment, post-decrement, and pre-decrement functions can %rd,[%sp]+ be used. %rd,[%sp]- %rd,-[%sp] Seiko Epson Corporation S1C17 CORE MANUAL (Rev. 1.2)
  • Page 24 Logical inversion between general-purpose registers (1's complement) %rd,%rs Supports conditional execution (/c: executed if C = 1, /nc: executed if C = 0). not/c not/nc Logical inversion of general-purpose register and immediate (1's complement) %rd,sign7 Seiko Epson Corporation S1C17 CORE MANUAL (REV. 1.2)
  • Page 25 32-bit data in which the eight high-order bits are set to 0 is written to the memory. During reading from a memo- ry, the eight high-order bits of the read data are ignored. Seiko Epson Corporation S1C17 CORE MANUAL (Rev. 1.2)
  • Page 26 Stack pointer Stack [%sp],[%sp+imm7] Stack with address post-incremented [%sp]+ Stack with address post-decremented [%sp]- Stack with address pre-decremented -[%sp] Unsigned immediate (numerals indicating bit length) imm3,imm5,imm7,imm13 Signed immediate (numerals indicating bit length) sign7,sign10 Seiko Epson Corporation S1C17 CORE MANUAL (REV. 1.2)
  • Page 27: Addressing Modes (without Ext Extension)

    Special register names are written as follows: Stack pointer Program counter The register names are always prefixed by “%” to discriminate them from symbol names, label names, and the like. Seiko Epson Corporation S1C17 CORE MANUAL (Rev. 1.2)
  • Page 28: Register Indirect Addressing

    The base address is decremented before a data transfer starts. This addressing mode is specified by enclosing the register name in brackets “[],” which is prefixed by “-.” The register name is actually written as -[%r0], -[%r1], ... -[%r7], or -[%sp]. Seiko Epson Corporation S1C17 CORE MANUAL (REV. 1.2)
  • Page 29: Register Indirect Addressing With Displacement

    PC. Also this addressing mode is used for the int and intl instructions that execute interrupt handler routines. Example: int Executes the interrupt handler of vector No. 3 (TTBR + 0xc). 0x03 Seiko Epson Corporation S1C17 CORE MANUAL (Rev. 1.2)
  • Page 30: Addressing Modes With Ext

    To extend the immediate to 24-bit quantity, enter two ext instructions directly before the target instruction. Example: ext imm13 imm13 %rd,[imm7] ; = ld %rd,[imm24] Extended immediate 20 19 imm13 imm13 (2) imm7 (3:0) Seiko Epson Corporation S1C17 CORE MANUAL (REV. 1.2)
  • Page 31: Extension Of Register Direct Addressing

    When extended by two ext instructions, rd = rs + imm16 X X X X X X X X Data 13 12 Immediate imm13 (2) imm13 (2:0) 0 0 0 0 0 0 0 0 Data + imm16 Seiko Epson Corporation S1C17 CORE MANUAL (Rev. 1.2)
  • Page 32: Extension Of Register Indirect Addressing

    Memory is accessed at the address derived by adding the 24-bit immediate specified by imm24 to the address specified by the rb register. Example: ext imm13 imm13 ld.b %rd,[%rb] ; = ld.b %rd,[%rb+imm24] Memory address pointer 13 12 Immediate imm13 imm13 (2) (10:0) Seiko Epson Corporation 5-10 S1C17 CORE MANUAL (REV. 1.2)
  • Page 33: Extension Of Register Indirect Addressing With Displacement

    The most significant bit “S” in the immediate that has been extended by the ext instruction is the sign, with which bits 23–21 are extended to become signed 21-bit data. The most significant bit in sign7 is handled as the MSB data of 7-bit data, and not as the sign. Seiko Epson Corporation S1C17 CORE MANUAL 5-11...
  • Page 34: Extension Of Pc Absolute Addressing

    To extend the immediate to 24-bit quantity, enter two ext instructions directly before the target instruction. Example: ext imm13 imm13 imm7 ; = jpa imm24 20 19 imm13 imm13 (2) imm7 Immediate (3:0) New address Seiko Epson Corporation 5-12 S1C17 CORE MANUAL (REV. 1.2)
  • Page 35: Data Transfer Instructions

    Unsigned byte data transfer 16 15 Byte data 16-bit data transfer 16 15 16-bit data 24/32-bit data transfer 24-bit data Refer to Chapter 3, “Data Formats,” for the data layout in the memory. Seiko Epson Corporation S1C17 CORE MANUAL 5-13 (Rev. 1.2)
  • Page 36: Logical Operation Instructions

    Instructions executable under NC condition (op = and, or, xor, not) op/nc %rd,%rs The instruction with the /nc switch will be executed only when the C flag has been cleared to 0. Example: xor/nc %rd,%rs Seiko Epson Corporation 5-14 S1C17 CORE MANUAL (REV. 1.2)
  • Page 37: Arithmetic Operation Instructions

    (op = add, add.a, adc, sub, sub.a, sbc, cmp, cmp.a, cmc) op/nc %rd,%rs The instruction with the /nc switch will be executed only when the C flag has been cleared to 0. Example: cmp/nc %rd,%rs Seiko Epson Corporation S1C17 CORE MANUAL 5-15 (Rev. 1.2)
  • Page 38: Shift And Swap Instructions

    Logical shift left sa Arithmetic shift right Sign bit The swap instruction replaces the contents of general-purpose registers with each other, as shown below. Byte 1 Byte 0 Byte 0 Byte 1 Seiko Epson Corporation 5-16 S1C17 CORE MANUAL (REV. 1.2)
  • Page 39: Branch And Delayed Branch Instructions

    S S S S S S S S S S S sign10 Current address Branch destination address The range of addresses to which jumped is (PC - 2,046) to (PC + 2,048). Seiko Epson Corporation S1C17 CORE MANUAL 5-17 (Rev. 1.2)
  • Page 40 The range of addresses to which jumped is (PC - 8,388,606) to (PC + 8,388,608). The above range of addresses to which jumped is a theoretical value, and is actually limited by the range of memory areas used. Seiko Epson Corporation 5-18 S1C17 CORE MANUAL...
  • Page 41 When the content of the rb register or the immediate is loaded into the PC, its least significant bit is always made 0. jpa %rb D(23:1) Branch destination address Seiko Epson Corporation S1C17 CORE MANUAL 5-19 (Rev. 1.2)
  • Page 42 Since these instructions are basically provided for the debug firmware, please do not use them in applica- tion programs. For details on the functionality of these instructions, refer to Section 6.5, “Debug Circuit.” Seiko Epson Corporation 5-20 S1C17 CORE MANUAL...
  • Page 43: Delayed Branch Instructions

    • The delayed branch instruction listed below can only be used with the ld.a %rd,%pc de- layed slot instruction. - jpr.d %rb/sign10 - jr*.d sign7 - jpa.d %rb/imm7 Seiko Epson Corporation S1C17 CORE MANUAL 5-21 (Rev. 1.2)
  • Page 44: System Control Instructions

    For details on HALT and SLEEP modes, refer to Section 6.4, “Power-Down Mode,” and the Technical Manual for each S1C17 model. For details on the interrupt control, refer to Section 6.3, “Interrupts.” Seiko Epson Corporation 5-22 S1C17 CORE MANUAL (REV. 1.2)
  • Page 45: Conversion Instructions

    16 15 8 bits 8 bits cv.ls %rd,%rs Extends the sign to convert 16-bit data into 32-bit data. 16 15 Word 16 15 S S S S S S S S S Seiko Epson Corporation S1C17 CORE MANUAL 5-23 (Rev. 1.2)
  • Page 46: Coprocessor Instructions

    The ld.ca and ld.cf instructions input the flag status from the coprocessor and set it to the PSR (C, V, Z, and N flags). The concrete commands and status of the coprocessor vary with each coprocessor connected to the chip. Refer to the user’s manual for the coprocessor used. Seiko Epson Corporation 5-24 S1C17 CORE MANUAL (REV. 1.2)
  • Page 47: Functions

    The processor is placed in HALT or SLEEP mode to reduce power consumption by executing the halt or slp instruction in the software (see Section 6.4). Normally the processor can be taken out of HALT or SLEEP mode by NMI or an external interrupt as well as initial reset. Seiko Epson Corporation S1C17 CORE MANUAL (Rev. 1.2)
  • Page 48: Program Execution

    Note: The pipelined operation shown above uses the internal memory. If external memory or low-speed external devices are used, one or more wait cycles may be inserted depending on the devices used, with the E stage kept waiting. Seiko Epson Corporation S1C17 CORE MANUAL (REV. 1.2)
  • Page 49: Execution Cycles And Flags

    – – %rd,%pc 1–2 – – – – – – %rd,[%sp] – – – – – – %rd,[%sp]+ – – – – – – %rd,[%sp]- – – – – – – %rd,-[%sp] Seiko Epson Corporation S1C17 CORE MANUAL (Rev. 1.2)
  • Page 50 ↔ ↔ – – – %rd,sign7 ↔ ↔ – – – %rd,%rs ↔ ↔ – – – not/c %rd,%rs ↔ ↔ – – – not/nc %rd,%rs ↔ ↔ – – – %rd,sign7 Seiko Epson Corporation S1C17 CORE MANUAL (REV. 1.2)
  • Page 51 – – – Coprocessor control – – – – – – %rd,%rs ld.cw %rd,imm7 ↔ ↔ ↔ ↔ – – ld.ca %rd,%rs %rd,imm7 ↔ ↔ ↔ ↔ – – ld.cf %rd,%rs %rd,imm7 Seiko Epson Corporation S1C17 CORE MANUAL (Rev. 1.2)
  • Page 52: Interrupts

    R0 save area (DBRAM: See Section 4.2.3) During debug interrupt handling, neither other interrupts nor multiple debug interrupts are accepted. They are kept pending until the debug interrupt handling currently underway finishes. Seiko Epson Corporation S1C17 CORE MANUAL (REV. 1.2)
  • Page 53: Vector Table

    PC. The processor thereby branches to the user’s initialization routine, in which it starts executing the program. The reset sequence has priority over all other processing. Seiko Epson Corporation S1C17 CORE MANUAL (Rev. 1.2)
  • Page 54: Address Misaligned Interrupt

    In the interrupt handler routine, the reti instruction should be executed at the end of processing. In the reti instruction, the saved data is restored from the stack in order of the PC and PSR, and the processing returns to the suspended instructions. Seiko Epson Corporation S1C17 CORE MANUAL (REV. 1.2)
  • Page 55: Software Interrupts

    Interrupt masked state still continues, so the next instruction will be executed before interrupts can be generated. Interrupt mask is released. Next instruction *2 The debug interrupt may occur even in the conditions (4) to (6). Seiko Epson Corporation S1C17 CORE MANUAL (Rev. 1.2)
  • Page 56: Power-down Mode

    When the interrupt has been disabled, the processor restarts the program from the instruction next to halt or slp after the processor is taken out of HALT or SLEEP mode. Seiko Epson Corporation 6-10 S1C17 CORE MANUAL...
  • Page 57: Debug Circuit

    Debugging is performed by connecting a serial ICE to the debug pins of the S1C17 Core and entering debug commands from the debugger being run on a personal computer. The tools listed below are required for debugging. • S1C17 Family Serial ICE (S5U1C17001H) • S1C17 Family C Compiler Package Seiko Epson Corporation S1C17 CORE MANUAL 6-11 (Rev. 1.2)
  • Page 58: Registers For Debugging

    1 (R/W): Enable 0 (R/W): Disable (default) DM: Debug Mode Bit Indicates the current operation mode of the processor (debug mode or user mode). 1 (R): Debug mode 0 (R): User mode (default) Seiko Epson Corporation 6-12 S1C17 CORE MANUAL (REV. 1.2)
  • Page 59 D[7:0] TXRXD[7:0]: Transmit/Receive Data This is the transmit/receive data register of the serial interface for the on-chip debug monitor used to set transmit data and to store received data. (Default: 0x00) Seiko Epson Corporation S1C17 CORE MANUAL 6-13 (Rev. 1.2)
  • Page 60: Details Of Instructions

    Register number (R0 = 0 ... R7 = 7) Delayed bit (0: Standard branch instruction, 1: Delayed branch instruction) Functions ←: Indicates that the right item is loaded or set to the left item. Addition Subtraction &: Seiko Epson Corporation S1C17 CORE MANUAL (Rev. 1.2)
  • Page 61 7 DETAILS OF INSTRUCTIONS Flags Interrupt level Interrupt enable flag Carry flag Overflow flag Zero flag Negative flag –: Not changed ↔: Set (1) or reset (0) Set (1) Reset (0) Seiko Epson Corporation S1C17 CORE MANUAL (REV. 1.2)
  • Page 62: Adc %rd, %rs

    (2) Addition of 32-bit data, data 1 = {r2, r1}, data 2 = {r4, r3}, result = {r2, r1} %r1,%r3 ; Addition of the low-order word %r2,%r4 ; Addition of the high-order word Seiko Epson Corporation S1C17 CORE MANUAL (Rev. 1.2)
  • Page 63: Adc %rd, Imm7

    “d” bit. In this case, extension of the immediate by the ext instruction cannot be performed. Example (1) adc %r0,0x7f ; r0 = r0 + 0x7f + C (2) ext 0x1ff %r1,0x7f ; r1 = r1 + 0xffff + C Seiko Epson Corporation S1C17 CORE MANUAL (REV. 1.2)
  • Page 64: Add %rd, %rs

    “d” bit. In this case, extension of the immediate by the ext instruction cannot be performed. Example (1) add %r0,%r0 ; r0 = r0 + r0 (2) ext 0x1fff %r1,%r2 ; r1 = r2 + 0x3fff Seiko Epson Corporation S1C17 CORE MANUAL (Rev. 1.2)
  • Page 65: Add %rd, Imm7

    “d” bit. In this case, extension of the immediate by the ext instruction cannot be performed. Example (1) add %r0,0x3f ; r0 = r0 + 0x3f (2) ext 0x1ff %r1,0x7f ; r1 = r1 + 0xffff Seiko Epson Corporation S1C17 CORE MANUAL (REV. 1.2)
  • Page 66: Add.a %rd, %rs

    “d” bit. In this case, extension of the immediate by the ext instruction cannot be performed. Example (1) add.a %r0,%r0 ; r0 = r0 + r0 (2) ext 0x7ff 0x1fff add.a %r1,%r2 ; r1 = r2 + 0xffffff Seiko Epson Corporation S1C17 CORE MANUAL (Rev. 1.2)
  • Page 67: Add.a %rd, Imm7

    “d” bit. In this case, extension of the immediate by the ext instruction cannot be performed. Example (1) add.a %r0,0x7f ; r0 = r0 + 0x7f (2) ext 0x1fff add.a %r1,0x7f ; r1 = r1 + 0xffffff Seiko Epson Corporation S1C17 CORE MANUAL (REV. 1.2)
  • Page 68: Add.a %sp, %rs

    ; sp = sp + r0 (2) ext 0x1ffc add.a %sp,%r2 ; sp = r2 + 0x3ffc Caution The 2 low-order bits of the addition results are always loaded to the SP as 0. Seiko Epson Corporation S1C17 CORE MANUAL (Rev. 1.2)
  • Page 69: Add.a %sp, Imm7

    ; sp = sp + 0x7c (2) ext 0x1fff add.a %sp,0x7c ; sp = sp + 0xffffc Caution The 2 low-order bits of the addition results are always loaded to the SP as 0. Seiko Epson Corporation 7-10 S1C17 CORE MANUAL (REV. 1.2)
  • Page 70: And %rd, %rs

    “d” bit. In this case, extension of the immediate by the ext instruction cannot be performed. Example (1) and %r0,%r0 ; r0 = r0 & r0 (2) ext 0x1fff %r1,%r2 ; r1 = r2 & 0x3fff Seiko Epson Corporation S1C17 CORE MANUAL 7-11 (Rev. 1.2)
  • Page 71: And %rd, Sign7

    “d” bit. In this case, extension of the immediate by the ext instruction cannot be performed. Example (1) and %r0,0x7e ; r0 = r0 & 0xfffe (2) ext 0x3f %r1,0x7f ; r1 = r1 & 0x1fff Seiko Epson Corporation 7-12 S1C17 CORE MANUAL (REV. 1.2)
  • Page 72: Brk

    The retd instruction must be used for return from the debug-handler routine. This instruction is provided for debug firmware. Do not use it in the user program. Example ; Executes the debug-handler routine Seiko Epson Corporation S1C17 CORE MANUAL 7-13 (Rev. 1.2)
  • Page 73: Call %rb

    If any other instruction is executed, the program may operate indeterminately. For the usable instructions, refer to the instruction list in the Appendix. Seiko Epson Corporation 7-14 S1C17 CORE MANUAL...
  • Page 74: Call Sign10

    If any other instruction is executed, the program may operate indeterminately. For the usable instructions, refer to the instruction list in the Appendix. Seiko Epson Corporation S1C17 CORE MANUAL 7-15...
  • Page 75: Calla %rb

    If any other instruction is executed, the program may operate indeterminately. For the usable instructions, refer to the instruction list in the Appendix. Seiko Epson Corporation 7-16 S1C17 CORE MANUAL...
  • Page 76: Calla Imm7

    If any other instruction is executed, the program may operate indeterminately. For the usable instructions, refer to the instruction list in the Appendix. Seiko Epson Corporation S1C17 CORE MANUAL 7-17...
  • Page 77: Cmc %rd, %rs

    In this case, the ext instruction can be used to extend the operand. The conditional execution instruction above sets/resets the flags (V, Z and N) according to the results if it is executed. Seiko Epson Corporation 7-18 S1C17 CORE MANUAL...
  • Page 78 %r0,%r1 ; Changes the flags according to the results of ; r0 - r1 - C. (2) ext 0x1fff %r1,%r2 ; Changes the flags according to the results of ; r2 - 0x1fff - C. Seiko Epson Corporation S1C17 CORE MANUAL 7-19 (Rev. 1.2)
  • Page 79: Cmc %rd, Sign7

    %r0,0x7f ; Changes the flags according to the results of ; r0 - 0x7f - C. (2) ext 0x1ff %r1,0x7f ; Changes the flags according to the results of ; r1 - 0xffff - C. Seiko Epson Corporation 7-20 S1C17 CORE MANUAL (REV. 1.2)
  • Page 80: Cmp %rd, %rs

    In this case, the ext instruction can be used to extend the operand. The conditional execution instruction above sets/resets the flags (V, Z and N) according to the results if it is executed. Seiko Epson Corporation S1C17 CORE MANUAL 7-21...
  • Page 81 %r0,%r1 ; Changes the flags according to the results of ; r0 - r1. (2) ext 0x1fff ; Changes the flags according to the results of %r1,%r2 ; r2 - 0x3fff. Seiko Epson Corporation 7-22 S1C17 CORE MANUAL (REV. 1.2)
  • Page 82: Cmp %rd, Sign7

    %r0,0x3f ; Changes the flags according to the results of ; r0 - 0x3f. (2) ext 0x1ff %r1,0x7f ; Changes the flags according to the results of ; r1 - 0xffff. Seiko Epson Corporation S1C17 CORE MANUAL 7-23 (Rev. 1.2)
  • Page 83: Cmp.a %rd, %rs

    In this case, the ext instruction can be used to extend the operand. The conditional execution instruction above sets/resets the flags (V and Z) according to the results if it is executed. Seiko Epson Corporation 7-24 S1C17 CORE MANUAL (REV. 1.2)
  • Page 84 ; Changes the flags according to the results of ; r0 - r1. (2) ext 0x1fff cmp.a %r1,%r2 ; Changes the flags according to the results of ; r2 - 0x3fff. Seiko Epson Corporation S1C17 CORE MANUAL 7-25 (Rev. 1.2)
  • Page 85: Cmp.a %rd, Imm7

    %r0,0x7f ; Changes the flags according to the results of ; r0 - 0x7f. (2) ext 0x1fff cmp.a %r1,0x7f ; Changes the flags according to the results of ; r1 - 0xffffff. Seiko Epson Corporation 7-26 S1C17 CORE MANUAL (REV. 1.2)
  • Page 86: Cv.ab %rd, %rs

    This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the “d” bit. Example When the R1 register contains 0x80 cv.ab %r0,%r1 ; r0 = 0xffff80 Seiko Epson Corporation S1C17 CORE MANUAL 7-27 (Rev. 1.2)
  • Page 87: Cv.al %rd, %rs

    This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the “d” bit. Example When the R1 register contains 0xff and the R0 register contains 0x0 cv.al %r0,%r1 ; r0 = 0xff0000 Seiko Epson Corporation 7-28 S1C17 CORE MANUAL (REV. 1.2)
  • Page 88: Cv.as %rd, %rs

    This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the “d” bit. Example When the R1 register contains 0x8000 cv.as %r0,%r1 ; r0 = 0xff8000 Seiko Epson Corporation S1C17 CORE MANUAL 7-29 (Rev. 1.2)
  • Page 89: Cv.la %rd, %rs

    This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the “d” bit. Example When the R1 register contains 0x800000 cv.la %r0,%r1 ; r0 = 0x000080 Seiko Epson Corporation 7-30 S1C17 CORE MANUAL (REV. 1.2)
  • Page 90: Cv.ls %rd, %rs

    This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the “d” bit. Example When the R1 register contains 0x008000 cv.ls %r0,%r1 ; r0 = 0x00ffff Seiko Epson Corporation S1C17 CORE MANUAL 7-31 (Rev. 1.2)
  • Page 91 ← Interrupt enabled ld.a %r0,%r1 ← Interrupt enabled ld.b %r2,%r3 ← Interrupt disabled ld %r4,%r5 ← Interrupt disabled ← Interrupt disabled add %r4,%r5 ← Interrupt disabled sub %r6,%r7 ← Interrupt enabled cmp %r0,%r1 Seiko Epson Corporation 7-32 S1C17 CORE MANUAL (REV. 1.2)
  • Page 92 ← Interrupt enabled ld.a %r0,%r1 ← Interrupt enabled ld.b %r2,%r3 ← Interrupt disabled ld %r4,%r5 ← Interrupt disabled ← Interrupt disabled add %r4,%r5 ← Interrupt disabled sub %r6,%r7 ← Interrupt enabled cmp %r0,%r1 Seiko Epson Corporation S1C17 CORE MANUAL 7-33 (Rev. 1.2)
  • Page 93: Ext Imm13

    If the interrupt handler routine is returned by simply executing the reti instruction, the previous ext instruction is invalidated. Therefore, it is necessary to modify the return address in that case. Seiko Epson Corporation 7-34 S1C17 CORE MANUAL...
  • Page 94: Halt

    HALT mode. Refer to the technical manual of each model for details of HALT mode. Example halt ; Sets the processor in HALT mode. Seiko Epson Corporation S1C17 CORE MANUAL 7-35 (Rev. 1.2)
  • Page 95: Int Imm5

    TTBR + 0x7c External maskable interrupt 0x1f The TTBR is the vector table base address. The reti instruction should be used for return from the handler routine. Example ; Generates an NMI. Seiko Epson Corporation 7-36 S1C17 CORE MANUAL (REV. 1.2)
  • Page 96: Intl Imm5, Imm3

    The altered IL bits are restored to the value before the intl instruction is executed when the interrupt handler routine is terminated by the reti instruction. Example intl 0x3,0x2 ; Generates an external maskable interrupt 0x3 ; and set the IL bits to 0x2. Seiko Epson Corporation S1C17 CORE MANUAL 7-37 (Rev. 1.2)
  • Page 97: Jpa %rb

    If any other instruction is executed, the program may operate indeterminately. For the usable instructions, refer to the instruction list in the Appendix. Seiko Epson Corporation 7-38 S1C17 CORE MANUAL...
  • Page 98: Jpa Imm7

    If any other instruction is executed, the program may operate indeterminately. For the usable instructions, refer to the instruction list in the Appendix. Seiko Epson Corporation S1C17 CORE MANUAL 7-39...
  • Page 99: Jpr %rb

    If any other instruction is executed, the program may operate indeterminately. For the usable instructions, refer to the instruction list in the Appendix. Seiko Epson Corporation 7-40 S1C17 CORE MANUAL...
  • Page 100: Jpr Sign10

    If any other instruction is executed, the program may operate indeterminately. For the usable instructions, refer to the instruction list in the Appendix. Seiko Epson Corporation S1C17 CORE MANUAL 7-41...
  • Page 101: Jreq Sign7

    If any other instruction is executed, the program may operate indeterminately. For the usable instructions, refer to the instruction list in the Appendix. Seiko Epson Corporation 7-42 S1C17 CORE MANUAL...
  • Page 102: Jrge Sign7

    If any other instruction is executed, the program may operate indeterminately. For the usable instructions, refer to the instruction list in the Appendix. Seiko Epson Corporation S1C17 CORE MANUAL 7-43...
  • Page 103: Jrgt Sign7

    If any other instruction is executed, the program may operate indeterminately. For the usable instructions, refer to the instruction list in the Appendix. Seiko Epson Corporation 7-44 S1C17 CORE MANUAL...
  • Page 104: Jrle Sign7

    If any other instruction is executed, the program may operate indeterminately. For the usable instructions, refer to the instruction list in the Appendix. Seiko Epson Corporation S1C17 CORE MANUAL 7-45...
  • Page 105: Jrlt Sign7

    If any other instruction is executed, the program may operate indeterminately. For the usable instructions, refer to the instruction list in the Appendix. Seiko Epson Corporation 7-46 S1C17 CORE MANUAL...
  • Page 106: Sign7

    If any other instruction is executed, the program may operate indeterminately. For the usable instructions, refer to the instruction list in the Appendix. Seiko Epson Corporation S1C17 CORE MANUAL 7-47...
  • Page 107: Jruge Sign7

    If any other instruction is executed, the program may operate indeterminately. For the usable instructions, refer to the instruction list in the Appendix. Seiko Epson Corporation 7-48 S1C17 CORE MANUAL...
  • Page 108: Jrugt Sign7

    If any other instruction is executed, the program may operate indeterminately. For the usable instructions, refer to the instruction list in the Appendix. Seiko Epson Corporation S1C17 CORE MANUAL 7-49...
  • Page 109: Jrule Sign7

    If any other instruction is executed, the program may operate indeterminately. For the usable instructions, refer to the instruction list in the Appendix. Seiko Epson Corporation 7-50 S1C17 CORE MANUAL...
  • Page 110: Jrult Sign7

    If any other instruction is executed, the program may operate indeterminately. For the usable instructions, refer to the instruction list in the Appendix. Seiko Epson Corporation S1C17 CORE MANUAL 7-51...
  • Page 111: Ld %rd, %rs

    (2) Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the “d” bit. ; r0 ← r1(15:0) Example %r0,%r1 Seiko Epson Corporation 7-52 S1C17 CORE MANUAL (REV. 1.2)
  • Page 112: Ld %rd, [%rb]

    The rb register and the displacement must specify a 16-bit boundary address (least significant bit = 0). Specifying an odd address causes an address misaligned interrupt. Note, however, that the data transfer is performed by setting the least significant bit of the address to 0. Seiko Epson Corporation S1C17 CORE MANUAL 7-53...
  • Page 113: Ld %rd, [%rb]

    The address increment/decrement sizes are listed below. When no ext is used (standard): 2 (16-bit size) When one ext is used (extension 1): imm13 When two ext are used (extension 2): imm24 Seiko Epson Corporation 7-54 S1C17 CORE MANUAL (REV. 1.2)
  • Page 114 The rb register and the immediate value must specify a 16-bit boundary address (least significant bit = 0). Specifying an odd address causes an address misaligned interrupt. Note, however, that the data transfer is performed by setting the least significant bit of the address to 0. Seiko Epson Corporation S1C17 CORE MANUAL 7-55...
  • Page 115: Ld %rd, [%sp + Imm7]

    The SP and the displacement must specify a 16-bit boundary address (least significant bit = 0). Specifying an odd address causes an address misaligned interrupt. Note, however, that the data transfer is performed by setting the least significant bit of the address to 0. Seiko Epson Corporation 7-56 S1C17 CORE MANUAL...
  • Page 116: Ld %rd, [imm7]

    The imm7 must specify a 16-bit boundary address (least significant bit = 0). Specifying an odd address causes an address misaligned interrupt. Note, however, that the data transfer is performed by setting the least significant bit of the address to 0. Seiko Epson Corporation S1C17 CORE MANUAL 7-57...
  • Page 117: Ld %rd, Sign7

    This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the “d” bit. In this case, extension of the immediate by the ext instruction cannot be performed. ; r0 ← 0xffff (r0 = 0x00ffff) Example %r0,0x7f Seiko Epson Corporation 7-58 S1C17 CORE MANUAL (REV. 1.2)
  • Page 118: Ld [%rb], %rs

    The rb register and the displacement must specify a 16-bit boundary address (least significant bit = 0). Specifying an odd address causes an address misaligned interrupt. Note, however, that the data transfer is performed by setting the least significant bit of the address to 0. Seiko Epson Corporation S1C17 CORE MANUAL 7-59...
  • Page 119: Ld [%rb]-, %rs

    The address increment/decrement sizes are listed below. When no ext is used (standard): 2 (16-bit size) When one ext is used (extension 1): imm13 When two ext are used (extension 2): imm24 Seiko Epson Corporation 7-60 S1C17 CORE MANUAL (REV. 1.2)
  • Page 120 The rb register and the immediate value must specify a 16-bit boundary address (least significant bit = 0). Specifying an odd address causes an address misaligned interrupt. Note, however, that the data transfer is performed by setting the least significant bit of the address to 0. Seiko Epson Corporation S1C17 CORE MANUAL 7-61...
  • Page 121: Ld [%sp + Imm7], %rs

    The SP and the displacement must specify a 16-bit boundary address (least significant bit = 0). Specifying an odd address causes an address misaligned interrupt. Note, however, that the data transfer is performed by setting the least significant bit of the address to 0. Seiko Epson Corporation 7-62 S1C17 CORE MANUAL...
  • Page 122: Ld [imm7], %rs

    The imm7 must specify a 16-bit boundary address (least significant bit = 0). Specifying an odd address causes an address misaligned interrupt. Note, however, that the data transfer is performed by setting the least significant bit of the address to 0. Seiko Epson Corporation S1C17 CORE MANUAL 7-63...
  • Page 123: Ld.a %rd, %pc

    PC value that is loaded into the rd register may not be the next instruction address to the ld.a instruction. • This instruction must be used as a delayed slot instruction for jr*.d, jpr.d or jpa.d. Seiko Epson Corporation 7-64 S1C17 CORE MANUAL...
  • Page 124: Ld.a %rd, %rs

    (2) Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the “d” bit. ; r0 ← r1 Example ld.a %r0,%r1 Seiko Epson Corporation S1C17 CORE MANUAL 7-65 (Rev. 1.2)
  • Page 125: Ld.a %rd, %sp

    Dst: Register direct %rd = %r0 to %r7 One cycle Description The content of the SP (24-bit data) is transferred to the rd register. ; r0 ← sp Example ld.a %r0,%sp Seiko Epson Corporation 7-66 S1C17 CORE MANUAL (REV. 1.2)
  • Page 126: Ld.a %rd, [%rb]

    The rb register and the displacement must specify a 32-bit boundary address (two least significant bits = 0). Specifying other address causes an address misaligned interrupt. Note, however, that the data transfer is performed by setting the two least significant bits of the address to 0. Seiko Epson Corporation S1C17 CORE MANUAL 7-67...
  • Page 127: Ld.a %rd, [%rb]

    The address increment/decrement sizes are listed below. When no ext is used (standard): 4 (32-bit size) When one ext is used (extension 1): imm13 When two ext are used (extension 2): imm24 Seiko Epson Corporation 7-68 S1C17 CORE MANUAL (REV. 1.2)
  • Page 128 The rb register and the immediate value must specify a 32-bit boundary address (two least significant bits = 0). Specifying other address causes an address misaligned interrupt. Note, however, that the data transfer is performed by setting the two least significant bits of the address to 0. Seiko Epson Corporation S1C17 CORE MANUAL 7-69...
  • Page 129: Ld.a %rd, [%sp]

    The displacement must specify a 32-bit boundary address (two least significant bits = 0). Specifying other address causes an address misaligned interrupt. Note, however, that the data transfer is performed by setting the two least significant bits of the address to 0. Seiko Epson Corporation 7-70 S1C17 CORE MANUAL...
  • Page 130: Ld.a %rd, [%sp]

    The address increment/decrement sizes are listed below. When no ext is used (standard): 4 (32-bit size) When one ext is used (extension 1): imm13 When two ext are used (extension 2): imm24 Seiko Epson Corporation S1C17 CORE MANUAL 7-71 (Rev. 1.2)
  • Page 131 The immediate must specify a 32-bit boundary address (two least significant bits = 0). Specifying other address causes an address misaligned interrupt. Note, however, that the data transfer is performed by setting the two least significant bits of the address to 0. Seiko Epson Corporation 7-72 S1C17 CORE MANUAL...
  • Page 132: Ld.a %rd, [%sp + Imm7]

    The SP and the displacement must specify a 32-bit boundary address (two least significant bits = 0). Specifying other address causes an address misaligned interrupt. Note, however, that the data transfer is performed by setting the two least significant bits of the address to 0. Seiko Epson Corporation S1C17 CORE MANUAL 7-73...
  • Page 133: Ld.a %rd, [imm7]

    The imm7 must specify a 32-bit boundary address (two least significant bits = 0). Specifying other address causes an address misaligned interrupt. Note, however, that the data transfer is performed by setting the two least significant bits of the address to 0. Seiko Epson Corporation 7-74 S1C17 CORE MANUAL...
  • Page 134: Ld.a %rd, Imm7

    This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the “d” bit. In this case, extension of the immediate by the ext instruction cannot be performed. ; r0 ← 0x00003f Example ld.a %r0,0x3f Seiko Epson Corporation S1C17 CORE MANUAL 7-75 (Rev. 1.2)
  • Page 135: Ld.a %sp, %rs

    The content of the rs register is transferred to the SP. ; sp ← r0 Example ld.a %sp,%r0 Caution In data transfer to the SP, the low-order two bits of the source data are always handled as 0. Seiko Epson Corporation 7-76 S1C17 CORE MANUAL (REV. 1.2)
  • Page 136: Ld.a %sp, Imm7

    Example ; sp ← 0x400 ld.a %sp,0x0 Caution In data transfer to the SP, the low-order two bits of the source data are always handled as 0. Seiko Epson Corporation S1C17 CORE MANUAL 7-77 (Rev. 1.2)
  • Page 137: Ld.a [%rb], %rs

    The rb register and the displacement must specify a 32-bit boundary address (two least significant bits = 0). Specifying other address causes an address misaligned interrupt. Note, however, that the data transfer is performed by setting the two least significant bits of the address to 0. Seiko Epson Corporation 7-78 S1C17 CORE MANUAL...
  • Page 138: Ld.a [%rb]-, %rs

    The address increment/decrement sizes are listed below. When no ext is used (standard): 4 (32-bit size) When one ext is used (extension 1): imm13 When two ext are used (extension 2): imm24 Seiko Epson Corporation S1C17 CORE MANUAL 7-79 (Rev. 1.2)
  • Page 139 The rb register and the immediate value must specify a 32-bit boundary address (two least significant bits = 0). Specifying other address causes an address misaligned interrupt. Note, however, that the data transfer is performed by setting the two least significant bits of the address to 0. Seiko Epson Corporation 7-80 S1C17 CORE MANUAL...
  • Page 140: Ld.a [%sp], %rs

    The SP and the displacement must specify a 32-bit boundary address (two least significant bits = 0). Specifying other address causes an address misaligned interrupt. Note, however, that the data transfer is performed by setting the two least significant bits of the address to 0. Seiko Epson Corporation S1C17 CORE MANUAL 7-81...
  • Page 141: Ld.a [%sp]+, %rs

    The address increment/decrement sizes are listed below. When no ext is used (standard): 4 (32-bit size) When one ext is used (extension 1): imm13 When two ext are used (extension 2): imm24 Seiko Epson Corporation 7-82 S1C17 CORE MANUAL (REV. 1.2)
  • Page 142 The SP and the immediate value must specify a 32-bit boundary address (two least significant bits = 0). Specifying other address causes an address misaligned interrupt. Note, however, that the data transfer is performed by setting the two least significant bits of the address to 0. Seiko Epson Corporation S1C17 CORE MANUAL 7-83...
  • Page 143: Ld.a [%sp + Imm7], %rs

    The SP and the displacement must specify a 32-bit boundary address (two least significant bits = 0). Specifying other address causes an address misaligned interrupt. Note, however, that the data transfer is performed by setting the two least significant bits of the address to 0. Seiko Epson Corporation 7-84 S1C17 CORE MANUAL...
  • Page 144: Ld.a [imm7], %rs

    The imm7 must specify a 32-bit boundary address (two least significant bits = 0). Specifying other address causes an address misaligned interrupt. Note, however, that the data transfer is performed by setting the two least significant bits of the address to 0. Seiko Epson Corporation S1C17 CORE MANUAL 7-85...
  • Page 145: Ld.b %rd, %rs

    (2) Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the “d” bit. ; r0 ← r1(7:0) sign-extended Example ld.b %r0,%r1 Seiko Epson Corporation 7-86 S1C17 CORE MANUAL (REV. 1.2)
  • Page 146: Ld.b %rd, [%rb]

    This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the “d” bit. In this case, extension of the immediate by the ext instruction cannot be performed. Seiko Epson Corporation S1C17 CORE MANUAL 7-87...
  • Page 147: Ld.b %rd, [%rb]

    The address increment/decrement sizes are listed below. When no ext is used (standard): 1 (byte size) When one ext is used (extension 1): imm13 When two ext are used (extension 2): imm24 Seiko Epson Corporation 7-88 S1C17 CORE MANUAL (REV. 1.2)
  • Page 148 This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the “d” bit. In this case, extension of the immediate by the ext instruction cannot be performed. Seiko Epson Corporation S1C17 CORE MANUAL 7-89...
  • Page 149: Ld.b %rd, [%sp + Imm7]

    “d” bit. In this case, extension of the immediate by the ext instruction cannot be performed. Example ; r0 ← [sp + 0x81] sign-extended ld.b %r0,[%sp + 0x1] Seiko Epson Corporation 7-90 S1C17 CORE MANUAL (REV. 1.2)
  • Page 150: Ld.b %rd, [imm7]

    This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the “d” bit. In this case, extension of the immediate by the ext instruction cannot be performed. Example %r0,[0x1] ; r0 ← [0x81] sign-extended ld.b Seiko Epson Corporation S1C17 CORE MANUAL 7-91 (Rev. 1.2)
  • Page 151: Ld.b [%rb], %rs

    This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the “d” bit. In this case, extension of the immediate by the ext instruction cannot be performed. Seiko Epson Corporation 7-92 S1C17 CORE MANUAL...
  • Page 152: Ld.b [%rb]+, %rs

    The address increment/decrement sizes are listed below. When no ext is used (standard): 1 (byte size) When one ext is used (extension 1): imm13 When two ext are used (extension 2): imm24 Seiko Epson Corporation S1C17 CORE MANUAL 7-93 (Rev. 1.2)
  • Page 153 This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the “d” bit. In this case, extension of the immediate by the ext instruction cannot be performed. Seiko Epson Corporation 7-94 S1C17 CORE MANUAL...
  • Page 154: Ld.b [%sp + Imm7], %rs

    “d” bit. In this case, extension of the immediate by the ext instruction cannot be performed. Example ; B[sp + 0x81] ← 8 low-order bits of r0 ld.b [%sp + 0x1],%r0 Seiko Epson Corporation S1C17 CORE MANUAL 7-95 (Rev. 1.2)
  • Page 155: Ld.b [imm7], %rs

    “d” bit. In this case, extension of the immediate by the ext instruction cannot be performed. Example ; B[0x81] ← 8 low-order bits of r0 ld.b [0x1],%r0 Seiko Epson Corporation 7-96 S1C17 CORE MANUAL (REV. 1.2)
  • Page 156: Ld.ca %rd, %rs

    The results are loaded to the rd register and the C, V, Z, and N flags in the PSR. (2) Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the “d” bit. Seiko Epson Corporation S1C17 CORE MANUAL 7-97 (Rev. 1.2)
  • Page 157: Ld.ca %rd, Imm7

    This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the “d” bit. In this case, extension of the immediate by the ext instruction cannot be performed. Seiko Epson Corporation 7-98 S1C17 CORE MANUAL...
  • Page 158: Ld.cf %rd, %rs

    C, V, Z, and N flags in the PSR. (2) Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the “d” bit. Seiko Epson Corporation S1C17 CORE MANUAL 7-99 (Rev. 1.2)
  • Page 159: Ld.cf %rd, Imm7

    This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the “d” bit. In this case, extension of the immediate by the ext instruction cannot be performed. Seiko Epson Corporation 7-100 S1C17 CORE MANUAL...
  • Page 160: Ld.cw %rd, %rs

    N flags in the PSR are not altered. (2) Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the “d” bit. Seiko Epson Corporation S1C17 CORE MANUAL 7-101 (Rev. 1.2)
  • Page 161: Ld.cw %rd, Imm7

    This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the “d” bit. In this case, extension of the immediate by the ext instruction cannot be performed. Seiko Epson Corporation 7-102 S1C17 CORE MANUAL...
  • Page 162: Ld.ub %rd, %rs

    (2) Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the “d” bit. ; r0 ← r1(7:0) zero-extended Example ld.ub %r0,%r1 Seiko Epson Corporation S1C17 CORE MANUAL 7-103 (Rev. 1.2)
  • Page 163: Ld.ub %rd, [%rb]

    This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the “d” bit. In this case, extension of the immediate by the ext instruction cannot be performed. Seiko Epson Corporation 7-104 S1C17 CORE MANUAL...
  • Page 164: Ld.ub %rd, [%rb]

    The address increment/decrement sizes are listed below. When no ext is used (standard): 1 (byte size) When one ext is used (extension 1): imm13 When two ext are used (extension 2): imm24 Seiko Epson Corporation S1C17 CORE MANUAL 7-105 (Rev. 1.2)
  • Page 165 This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the “d” bit. In this case, extension of the immediate by the ext instruction cannot be performed. Seiko Epson Corporation 7-106 S1C17 CORE MANUAL...
  • Page 166: Ld.ub %rd, [%sp + Imm7]

    “d” bit. In this case, extension of the immediate by the ext instruction cannot be performed. Example %r0,[%sp + 0x1] ; r0 ← [sp + 0x81] zero-extended ld.ub Seiko Epson Corporation S1C17 CORE MANUAL 7-107 (Rev. 1.2)
  • Page 167: Ld.ub %rd, [imm7]

    This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the “d” bit. In this case, extension of the immediate by the ext instruction cannot be performed. Example %r0,[0x1] ; r0 ← [0x81] zero-extended ld.ub Seiko Epson Corporation 7-108 S1C17 CORE MANUAL (REV. 1.2)
  • Page 168: Nop

    (2) Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the “d” bit. Example ; Waits 2 cycles Seiko Epson Corporation S1C17 CORE MANUAL 7-109 (Rev. 1.2)
  • Page 169: Not %rd, %rs

    “d” bit. In this case, extension of the immediate by the ext instruction cannot be performed. Example When r1 = 0x555555 %r0,%r1 ; r0 = 0x00aaaa Seiko Epson Corporation 7-110 S1C17 CORE MANUAL (REV. 1.2)
  • Page 170: Not %rd, Sign7

    “d” bit. In this case, extension of the immediate by the ext instruction cannot be performed. Example (1) not %r0,0x3f ; r0 = 0x00ffc0 (2) ext 0x1ff %r1,0x7f ; r1 = 0x000000 Seiko Epson Corporation S1C17 CORE MANUAL 7-111 (Rev. 1.2)
  • Page 171: Or %rd, %rs

    “d” bit. In this case, extension of the immediate by the ext instruction cannot be performed. Example (1) or %r0,%r0 ; r0 = r0 | r0 (2) ext 0x1fff %r1,%r2 ; r1 = r2 | 0x3fff Seiko Epson Corporation 7-112 S1C17 CORE MANUAL (REV. 1.2)
  • Page 172: Or %rd, Sign7

    “d” bit. In this case, extension of the immediate by the ext instruction cannot be performed. Example (1) or %r0,0x7e ; r0 = r0 | 0xfffe (2) ext 0xff %r1,0x7f ; r1 = r1 | 0x7fff Seiko Epson Corporation S1C17 CORE MANUAL 7-113 (Rev. 1.2)
  • Page 173: Ret

    If any other instruction is executed, the program may operate indeterminately. For the usable instructions, refer to the instruction list in the Appendix. Seiko Epson Corporation 7-114 S1C17 CORE MANUAL...
  • Page 174 (DBRAM) when an debug interrupt occurred to the respective registers, and return from the debug interrupt handler routine. This instruction is provided for debug firmware. Do not use it in the user program. Example retd ; Return from a debug interrupt handler routine Seiko Epson Corporation S1C17 CORE MANUAL 7-115 (Rev. 1.2)
  • Page 175: Reti

    Interrupts are masked in intervals between the reti.d instruction and the next instruction, so no interrupts occur. Example reti ; Return from a interrupt handler routine Seiko Epson Corporation 7-116 S1C17 CORE MANUAL (REV. 1.2)
  • Page 176: Sa %rd, %rs

    (after execution) S ... S (2) Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the “d” bit included. Seiko Epson Corporation S1C17 CORE MANUAL 7-117 (Rev. 1.2)
  • Page 177: Sa %rd, Imm7

    This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the “d” bit included. In this case, extension of the immediate by the ext instruction cannot be performed. Seiko Epson Corporation 7-118 S1C17 CORE MANUAL...
  • Page 178: Sbc %rd, %rs

    (2) Subtraction of 32-bit data data 1 = {r2, r1}, data2 = {r4, r3}, result = {r2, r1} %r1,%r3 ; Subtraction of the low-order word %r2,%r4 ; Subtraction of the high-order word Seiko Epson Corporation S1C17 CORE MANUAL 7-119 (Rev. 1.2)
  • Page 179: Sbc %rd, Imm7

    “d” bit. In this case, extension of the immediate by the ext instruction cannot be performed. Example (1) sbc %r0,0x7f ; r0 = r0 - 0x7f - C (2) ext 0x1ff %r1,0x7f ; r1 = r1 - 0xffff - C Seiko Epson Corporation 7-120 S1C17 CORE MANUAL (REV. 1.2)
  • Page 180: Sl %rd, %rs

    (after execution) (2) Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the “d” bit included. Seiko Epson Corporation S1C17 CORE MANUAL 7-121 (Rev. 1.2)
  • Page 181: Sl %rd, Imm7

    This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the “d” bit included. In this case, extension of the immediate by the ext instruction cannot be performed. Seiko Epson Corporation 7-122 S1C17 CORE MANUAL...
  • Page 182: Slp

    SLEEP mode. Refer to the technical manual of each model for details of SLEEP mode. Example ; The processor is placed in SLEEP mode. Seiko Epson Corporation S1C17 CORE MANUAL 7-123 (Rev. 1.2)
  • Page 183: Sr %rd, %rs

    (after execution) (2) Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the “d” bit included. Seiko Epson Corporation 7-124 S1C17 CORE MANUAL (REV. 1.2)
  • Page 184: Sr %rd, Imm7

    This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the “d” bit included. In this case, extension of the immediate by the ext instruction cannot be performed. Seiko Epson Corporation S1C17 CORE MANUAL 7-125...
  • Page 185: Sub %rd, %rs

    “d” bit. In this case, extension of the immediate by the ext instruction cannot be performed. Example (1) sub %r0,%r0 ; r0 = r0 - r0 (2) ext 0x1fff %r1,%r2 ; r1 = r2 - 0x3fff Seiko Epson Corporation 7-126 S1C17 CORE MANUAL (REV. 1.2)
  • Page 186: Sub %rd, Imm7

    “d” bit. In this case, extension of the immediate by the ext instruction cannot be performed. Example (1) sub %r0,0x3f ; r0 = r0 - 0x3f (2) ext 0x1ff %r1,0x7f ; r1 = r1 - 0xffff Seiko Epson Corporation S1C17 CORE MANUAL 7-127 (Rev. 1.2)
  • Page 187: Sub.a %rd, %rs

    “d” bit. In this case, extension of the immediate by the ext instruction cannot be performed. Example (1) sub.a %r0,%r0 ; r0 = r0 - r0 (2) ext 0x7ff 0x1fff sub.a %r1,%r2 ; r1 = r2 - 0xffffff Seiko Epson Corporation 7-128 S1C17 CORE MANUAL (REV. 1.2)
  • Page 188: Sub.a %rd, Imm7

    “d” bit. In this case, extension of the immediate by the ext instruction cannot be performed. Example (1) sub.a %r0,0x7f ; r0 = r0 - 0x7f (2) ext 0x1fff sub.a %r1,0x7f ; r1 = r1 - 0xffffff Seiko Epson Corporation S1C17 CORE MANUAL 7-129 (Rev. 1.2)
  • Page 189: Sub.a %sp, %rs

    ; sp = sp - r0 (2) ext 0x1ffc sub.a %sp,%r2 ; sp = r2 - 0x3ffc Caution The 2 low-order bits of the subtruction results are always loaded to the SP as 0. Seiko Epson Corporation 7-130 S1C17 CORE MANUAL (REV. 1.2)
  • Page 190: Sub.a %sp, Imm7

    ; sp = sp - 0x7c (2) ext 0x1fff sub.a %sp,0x7c ; sp = sp - 0xffffc Caution The 2 low-order bits of the subtruction results are always loaded to the SP as 0. Seiko Epson Corporation S1C17 CORE MANUAL 7-131 (Rev. 1.2)
  • Page 191: Swap %rd, %rs

    This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the “d” bit. Example When r1 = 0x123456 ; 0x005634 → r2 swap %r2,%r1 Seiko Epson Corporation 7-132 S1C17 CORE MANUAL (REV. 1.2)
  • Page 192: Xor %rd, %rs

    “d” bit. In this case, extension of the immediate by the ext instruction cannot be performed. Example (1) xor %r0,%r0 ; r0 = r0 ^ r0 (2) ext 0x1fff %r1,%r2 ; r1 = r2 ^ 0x3fff Seiko Epson Corporation S1C17 CORE MANUAL 7-133 (Rev. 1.2)
  • Page 193: Xor %rd, Sign7

    “d” bit. In this case, extension of the immediate by the ext instruction cannot be performed. Example (1) xor %r0,0x7e ; r0 = r0 ^ 0xfffe (2) ext 0x1ff %r1,0x7f ; r1 = r1 ^ 0xffff Seiko Epson Corporation 7-134 S1C17 CORE MANUAL (REV. 1.2)
  • Page 194 Appendix List of S1C17 Core Instructions Symbols in the Instruction List S1C17 Core Instruction Set Registers/Register Data Flags %rd, rd: A general-purpose register (R0–R7) used as the destination register or its contents Interrupt level %rs, rs: A general-purpose register (R0–R7) used as the source register or its contents Interrupt enable flag %rb, rb: A general-purpose register (R0–R7) that has stored a base address to be accessed in...
  • Page 195 Data Transfer Instructions (1) S1C17 Core Instruction Set Mnemonic Flags Code Function Cycle Opcode Operand ld.b %rd, %rs rd(7:0)←rs(7:0), rd(15:8)←rs(7), rd(23:16)←0 – – – – – – – %rd, [%rb] rd(7:0)←B[rb], rd(15:8)←B[rb](7), rd(23:16)←0 1, 2 – – – – – –...
  • Page 196 Data Transfer Instructions (2) S1C17 Core Instruction Set Mnemonic Flags Code Function Cycle Opcode Operand [%sp+imm7], %rs imm7 W[sp+imm7]←rs(15:0) – – – – – – [imm7], %rs imm7 W[imm7]←rs(15:0) – – – – – – ld.a %rd, %rs rd(23:0)←rs(23:0) – –...
  • Page 197 Integer Arithmetic Operation Instructions (1) S1C17 Core Instruction Set Mnemonic Flags Code Function Cycle Opcode Operand %rd, %rs rd(15:0)←rd(15:0)+rs(15:0), rd(23:16)←0 – – ↔ ↔ ↔ ↔ add/c %rd, %rs rd(15:0)←rd(15:0)+rs(15:0), rd(23:16)←0 if C = 1 (nop if C = 0) –...
  • Page 198 Integer Arithmetic Operation Instructions (2) S1C17 Core Instruction Set Mnemonic Flags Code Function Cycle Opcode Operand ↔ ↔ cmp.a %rd, %rs rd(23:0)-rs(23:0) – – – – cmp.a/c %rd, %rs rd(23:0)-rs(23:0) if C = 1 (nop if C = 0) – –...
  • Page 199 Branch Instructions S1C17 Core Instruction Set Mnemonic Flags Cycle Code Function Opcode Operand jpr / jpr.d sign10 sign10 pc←pc+2+sign11; sign11={sign10,0} (*3) – – – – – – – pc←pc+2+rb (*3) – – – – – – – – jpa / jpa.d imm7 imm7 pc←imm7 (*3)
  • Page 200 Shift and Swap Instructions S1C17 Core Instruction Set Mnemonic Flags Code Function Cycle Opcode Operand ↔ ↔ ↔ %rd, %rs Logical shift to right; rd(15:0)←rd(15:0)>>rs(15:0), rd(23:16)←0, zero enters to MSB (*1) – – – – %rd, imm7 imm7 Logical shift to right; rd(15:0)←rd(15:0)>>imm7, rd(23:16)←0, zero enters to MSB (*1) –...
  • Page 201 Coprocessor Interface Instructions S1C17 Core Instruction Set Mnemonic Flags Code Function Cycle Opcode Operand ld.cw %rd, %rs co_dout0←rd, co_dout1←rs – – – – – – – %rd, imm7 imm7 co_dout0←rd, co_dout1←imm7 – – – – – – ld.ca %rd, %rs co_dout0←rd, co_dout1←rs, rd←co_din, psr(C, V, Z, N)←co_cvzn –...
  • Page 202 REVISION HISTORY Revision History Code No. Page Contents 410905900 New establishment 410905901 Made an overall revision. 410905902 6-10 Corrected the description in “Canceling HALT or SLEEP mode.” 7-32, 7-33 Added “Caution” to the di and ei instruction pages.
  • Page 203 Phone: +49-89-14005-0 Fax: +49-89-14005-110 Keyuan South RD (Shenzhen bay), Nanshan District, Shenzhen 518054, CHINA Phone: +86-10-3299-0588 Fax: +86-10-3299-0560 EPSON TAIWAN TECHNOLOGY & TRADING LTD. 14F, No. 7, Song Ren Road, Taipei 110, TAIWAN Phone: +886-2-8786-6688 Fax: +886-2-8786-6660 EPSON SINGAPORE PTE., LTD.

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