Epson S1C31D50 Technical Instructions page 112

7.7.12. PD Port Group
The PD port group consists of four ports PD0–PD5 and two ports PD0–PD1 are configured as
debugging function ports at initialization. These four ports support the GPIO function.
Register name Bit
PPORTPDDAT 15–14
(PD Port Data 13–8
Register)
7–6
5–0
PPORTPDIOEN 15–14
(PD Port Enable 13–8
Register)
7–4
3–0
PPORTPDRCTL 15–14
(PD Port Pull-
13–8
up/down Control
7–6
Register)
5–0
PPORTPDINTF 15–0
PPORTPDINTCTL
PPORTPDCHATEN
PPORTPDMODSEL 15–8
(PD Port Mode 7–6
Select Register) 5–0
PPORTPDFNCSEL 15–12
(PD Port Function
11–10
Select Register) 9–8
7–6
5–4
3–2
1–0
PdSELy = 0
Port
name
GPIO
Peripheral
PD0 PD0 CPU core
PD1 PD1 CPU core
PD2 PD2
PD3 PD3
PD4 PD4
PD5 PD5
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
Table 7.7.12.1 Control Registers for Pd Port Group
Bit name Initial
–
PDOUT[5:0]
–
PDIN[5:0]
–
PDIEN[5:0]
–
PDOEN[5:0]
–
PDPDPU[5:0]
–
PDREN[5:0]
– 0x0000
– 0x00
–
PDSEL[5:0]
– 0x00
PD5MUX[1:0]
PD4MUX[1:0]
PD3MUX[1:0]
PD2MUX[1:0]
PD1MUX[1:0]
PD0MUX[1:0]
Table 7.7.12.2 Pd Port Group Function Assignment
PDyMUX = 0x0 PDyMUX = 0x1
(Function 0) (Function 1)
Pin Peripheral Peripheral Peripheral
SWCLK –
SWD –
– – –
– – –
– – –
– – –
Seiko Epson Corporation
Reset R/W
0x0 – R
0x0 H0 R/W
0x0 – R
x H0 R
0x0 – R
0x0 H0 R/W
0x0 – R
0x0 H0 R/W
0x0 – R
0x0 H0 R/W
0x0 – R
0x0 H0 R/W
– R
– R
0x0 – R
0x3 H0 R/W
– R
0x0 H0 R/W
0x0 H0 R/W
0x0 H0 R/W
0x0 H0 R/W
0x0 H0 R/W
0x0 H0 R/W
PDSELy = 1
PDyMUX = 0x2
(Function 2)
– –
– –
– CLG
– CLG
– –
– –
Remarks
–
–
–
–
–
–
PDyMUX = 0x0
(Function 0)
Pin Peripheral Pin
– – –
– – –
OSC3 – –
OSC4 – –
– – –
– – –
7-25