Page 1 CMOS 32-BIT SINGLE CHIP MICROCONTROLLER S1C33L26 Technical Manual Rev.1.1...
Page 2 No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability...
Page 3 Configuration of product number Devices 33209 00E1 Packing specifications 00 : Besides tape & reel 0A : TCP BL 2 directions 0B : Tape & reel BACK 0C : TCP BR 2 directions 0D : TCP BT 2 directions 0E : TCP BD 2 directions 0F : Tape &...
Page 4 5.1.3 Initial Reset Sequence ..................5-2 5.1.4 Initial Reset Status ....................5-2 5.1.5 Precautions to be Taken during Initial Reset ............5-3 5.2 NMI Input .........................5-3 5.2.1 #NMI Pin ......................5-4 5.2.2 NMI by the Watchdog Timer ................5-4 Seiko Epson Corporation S1C33L26 TECHNICAL MANUAL...
Page 5 CMU Write Protect Register (CMU_PROTECT) ............... 6-27 7 Prescaler (PSC) ......................7-1 7.1 PSC Module Overview .....................7-1 7.2 Control Register Details ....................7-1 PSC Control Register (PSC_CTL)..................... 7-1 8 Real-Time Clock (RTC) ....................8-1 8.1 RTC Module Overview .....................8-1 8.2 RTC Counters ........................8-2 Seiko Epson Corporation S1C33L26 TECHNICAL MANUAL...
Page 6 10.4 Configuration of SDRAM ....................10-2 10.4.1 SDRAM Area ....................10-2 10.4.2 SDRAM Size and Access Condition Settings ..........10-2 10.5 Control and Operation of SDRAM Interface ..............10-7 10.5.1 Initializing SDRAM ..................10-7 10.5.2 SDRAM Commands..................10-9 10.5.3 SDRAM Bus Operations .................10-9 Seiko Epson Corporation S1C33L26 TECHNICAL MANUAL...
Page 7 13.1 DMAC Module Overview ....................13-1 13.2 DMAC Operating Clock ....................13-1 13.3 Programming Control Information .................13-2 13.3.1 Setting the Base Address ................13-2 13.3.2 Control Information ..................13-2 13.3.3 Auto-Reload Data ...................13-6 13.4 DMAC Invocation ......................13-6 13.5 Operation of DMAC .......................13-8 Seiko Epson Corporation S1C33L26 TECHNICAL MANUAL...
Page 8 T16A5 Ch.x Comparator/Capture A Data Registers (T16A_CCAx) ........15-15 T16A5 Ch.x Comparator/Capture B Data Registers (T16A_CCBx) ........15-15 T16A5 Ch.x Comparator/Capture Interrupt Enable Registers (T16A_IENx) ......15-16 T16A5 Ch.x Comparator/Capture Interrupt Flag Registers (T16A_IFLGx) ......15-16 Seiko Epson Corporation S1C33L26 TECHNICAL MANUAL...
Page 9 18.1 USI Module Overview ....................18-1 18.2 USI Pins ........................18-2 18.3 USI Clock Sources ......................18-2 18.4 USI Module Settings ....................18-4 18.4.1 USI Module Software Reset ................18-4 18.4.2 Interface Mode ....................18-4 18.4.3 General Settings for All Interface Modes ............18-4 Seiko Epson Corporation S1C33L26 TECHNICAL MANUAL...
Page 10 C Mode ................19-13 19.5.4 Data Transmission in LCD SPI Mode .............19-23 19.5.5 Data Transfer in LCD Parallel Mode ...............19-24 19.6 Receive Errors......................19-27 19.7 USIL Interrupts and DMA .....................19-28 19.7.1 Interrupts in UART Mode ................19-28 Seiko Epson Corporation S1C33L26 TECHNICAL MANUAL...
Page 11 20.8 IrDA Interface .......................20-18 20.8.1 Outline of IrDA Interface .................20-18 20.8.2 Setting IrDA Interface ..................20-19 20.8.3 Control and Operation of IrDA Interface ............20-20 20.9 FSIO Interrupts and DMA .....................20-21 20.9.1 Interrupts ......................20-21 20.9.2 DMA Transfer ....................20-22 Seiko Epson Corporation viii S1C33L26 TECHNICAL MANUAL...
Page 12 23.1 CARD Module Overview ....................23-1 23.2 CARD Output Pins ......................23-1 23.3 Card Interface Control Signals ..................23-1 24 I/O Ports (GPIO) ......................24-1 24.1 GPIO Module Overview ....................24-1 24.2 Input/Output Pin Function Selection (Port MUX) ............24-2 Seiko Epson Corporation S1C33L26 TECHNICAL MANUAL...
Page 13 P9[3:0] Port Function Select Register (PMUX_P9_03) ............24-36 P9[7:4] Port Function Select Register (PMUX_P9_47) ............24-37 PA[3:0] Port Function Select Register (PMUX_PA_03) ............24-38 PA[6:4] Port Function Select Register (PMUX_PA_46) ............24-38 PB[3:0] Port Function Select Register (PMUX_PB_03) ............24-39 Seiko Epson Corporation S1C33L26 TECHNICAL MANUAL...
Page 14 26.6.2 Main Window Display Start Address and Virtual Screen Settings ....26-29 26.6.3 Writing Display Data ..................26-31 26.6.4 Inverting and Blanking the Display ..............26-31 26.6.5 Picture-in-Picture Plus and Sub-Window ............26-31 26.7 LCDC Interrupt ......................26-34 26.8 Power Save ........................26-34 Seiko Epson Corporation S1C33L26 TECHNICAL MANUAL...
Page 15 27.5.7 RECT Command (Rectangle Drawing) ............27-31 27.5.8 TRI_FILL Command (Solid Filled Triangle Drawing) ........27-33 27.5.9 RECT_FILL Command (Solid Filled Rectangle Drawing) ......27-35 27.5.10 QUAD_FILL Command (Solid Filled Quadrilateral Drawing) .......27-37 27.5.11 CIRCLE Command (Circle Drawing) ............27-39 Seiko Epson Corporation S1C33L26 TECHNICAL MANUAL...
Page 16 EPbIntStat (EPb Interrupt Status) ................... 28-30 EPcIntStat (EPc Interrupt Status) .................... 28-31 EPdIntStat (EPd Interrupt Status) ................... 28-32 MainIntEnb (Main Interrupt Enable)..................28-32 SIE_IntEnb (SIE Interrupt Enable)................... 28-33 EPrIntEnb (EPr Interrupt Enable) .................... 28-33 Seiko Epson Corporation S1C33L26 TECHNICAL MANUAL xiii...
Page 17 EPnRdRemain_H (EPn FIFO Read Remain HIGH) ..............28-55 EPnRdRemain_L (EPn FIFO Read Remain LOW) ..............28-55 EPnWrRemain_H (EPn FIFO Write Remain HIGH) ..............28-55 EPnWrRemain_L (EPn FIFO Write Remain LOW) ..............28-55 DescAdrs_H (Descriptor Address HIGH) ................28-55 Seiko Epson Corporation S1C33L26 TECHNICAL MANUAL...
Page 18 31.8.2 SRAMC AC Characteristics ................31-7 31.8.3 SDRAMC AC Characteristics ................31-8 31.8.4 USI/USIL AC Characteristics .................31-11 31.8.5 LCDC AC Characteristics ................31-13 31.8.6 #STBY AC Characteristics ................31-24 31.9 USB DC and AC Characteristics ..................31-24 32 Basic External Connection Diagram ................32-1 Seiko Epson Corporation S1C33L26 TECHNICAL MANUAL...
Page 19 D.3.3 EEPROM Data ....................AP-D-5 D.4 PC RS232C Boot ......................AP-D-6 D.4.1 Configuration of PC RS232C Boot System ..........AP-D-6 D.4.2 PC RS232C Boot Sequence ................ AP-D-6 D.4.3 Transfer Data ....................AP-D-8 Revision History Seiko Epson Corporation S1C33L26 TECHNICAL MANUAL...
Page 20 These functions help reduce CPU load for ADPCM audio data playback processing. Also the embedded I S inter- face module is capable of being used to connect an external audio DAC. The S1C33L26 has adopted the EPSON SoC (System on Chip) design technology using 0.18 µm low power CMOS process to install these features. Features The features of the S1C33L26 are outlined below.
Page 21 • Image data block transfer - Rectangle area copy within VRAM - Data copy between VRAM and other memory • Drawing effects - Clipping draw - Line width setting - Drawing color setting with transparency feature - Fill/Mesh/Rewrite/XOR Seiko Epson Corporation S1C33L26 TECHNICAL MANUAL...
Page 22 - Multiplication rate: • OSC1 oscillator circuit - Crystal oscillation: 32.768 kHz typ. - External clock input: 32.768 kHz typ. Interrupt Controller (ITC) • Five non-maskable interrupts • 31 maskable interrupts (including four software interrupts) Seiko Epson Corporation S1C33L26 TECHNICAL MANUAL...
Page 23 - Can generate receive buffer full, transmit buffer empty, and receive error interrupts. - Supports DMA transfer. • SPI mode - Supports both master and slave modes. - Data length: 8 or 9 bits (master mode), 8 bits fixed (slave mode) Seiko Epson Corporation S1C33L26 TECHNICAL MANUAL...
Page 24 • Supports IrDA1.0-equivalent communications by software control or using an external IrDA driver. • Contains a baud-rate generator (12-bit programmable timer). • Can generate receive buffer full, transmit buffer empty, and receive error interrupts. • Supports DMA transfer. Seiko Epson Corporation S1C33L26 TECHNICAL MANUAL...
Page 25 • Supports auto negotiation function. • Supports control, bulk, isochronous and interrupt transfers. • Supports four general-purpose endpoints and endpoint 0 (control). • Embedded 1K-byte programmable FIFO • Can generate USB interrupts. • Supports DMA transfer. Seiko Epson Corporation S1C33L26 TECHNICAL MANUAL...
Page 26 1.7 V to 1.9 V (1.8 V typ.) when a ceramic resonator is used. * LV = PLLV = RTCV The S1C33L26 does not support 5 V tolerant I/O. Operating Temperatures • -40 to 85°C • 0 to 70°C when the USB module and a ceramic resonator are used.
Page 27 FSIO (2 ch) T8F (4 ch) T8 (4 ch) T16A5 (2 ch) T16P ADC10 REMC LCDC (Reg.) DMAC SDRAMC SRAMC (Reg.) (Reg.) (Reg.) (Reg.) (Reg.) BBRAM (16 bytes) RTCV Figure 1. 2.1 Block Diagram Seiko Epson Corporation S1C33L26 TECHNICAL MANUAL...
Page 28 1 OVERVIEW Pin Descriptions 1.3.1 Pin Arrangement The S1C33L26 comes in a TQFP15-128pin, TQFP24-144pin or PFBGA12U-180 package. TQFP15-128pin package P97 (FPDAT7/LCD_D7) P96 (FPDAT6/LCD_D6) A17/DQMH (P50/#SDCS) #CE7 P95 (FPDAT5/LCD_D5) A0/#BSL P94 (FPDAT4/LCD_D4) P93 (FPDAT3/LCD_D3/#SRDY0) A1/SDA0 A2/SDA1 P92 (FPDAT2/LCD_D2/SCLK0) A3/SDA2 P91 (FPDAT1/LCD_D1/SOUT0)
Page 29 P72 (AIN2/PWM_EXCL) (P56) #WRH/#BSH P73 (AIN3) (P20) SDCKE P74 (AIN4) (P21) SDCLK P75 (AIN5/#WAIT/#ADTRIG) (P52/#CE5) #CE9 #STBY (PA4/T16A_ATMA_1/REMC_O) A24 WAKEUP (PA5/T16A_ATMB_1/REMC_I) A25 A18/#SDWE RTCCLKO A19/#SDCAS RTCCLKI A20/#SDRAS RTCV Figure 1. 3.1.2 Pin Arrangement (TQFP24-144pin) Seiko Epson Corporation 1-10 S1C33L26 TECHNICAL MANUAL...
Page 30 LCD_D4 LCD_D7 REMC_I #ADTRIG SOUT0 RTCCLKI RTCCLKO PLLV MCLKI MCLKO AIN4 AIN2 AIN0 FPSHIFT FPDAT0 FPDAT3 FPDAT6 PWM_EXCL T16A_EXCL_0 USIL_DI LCD_D0 LCD_D3 LCD_D6 N.C. SIN0 #SRDY0 N.C. Figure 1. 3.1.3 Pin Arrangement (PFBGA12U-180) Seiko Epson Corporation 1-11 S1C33L26 TECHNICAL MANUAL...
Page 31 1 OVERVIEW 1.3.2 Pin Functions The tables below list the S1C33L26 pin functions. Notes: • Pin name - The # prefixed to pin names indicates that the pin inputs/outputs an active low signal. - The pin names listed in boldface denote the default pin (signal) name.
Page 32 Address bus A7 / SDRAM address A6 25 A8/SDA7 Address bus A8 / SDRAM address A7 26 A9/SDA8 Address bus A9 / SDRAM address A8 27 A10/SDA9 Address bus A10 / SDRAM address A9 Seiko Epson Corporation 1-13 S1C33L26 TECHNICAL MANUAL...
Page 33 Schmitt (en)* (default) i/o I/O port * The #CE10 pull-up resistor is enabled (en) when the BOOT pin is set to 0 or disabled (dis) when the BOOT pin is set to 1. Seiko Epson Corporation 1-14 S1C33L26 TECHNICAL MANUAL...
Page 34 S serial bit clock output PWM_H o T16P PWM_H signal output I/o I/O port (default) #SRDY0 i/o FSIO Ch.0 ready signal input/output (see Table 1.3.2.10.) I2S_MCLK S master clock output PWM_L o T16P PWM_L signal output Seiko Epson Corporation 1-15 S1C33L26 TECHNICAL MANUAL...
Page 35 AIN4 ADC10 Ch.4 analog input Analog 24 P75 Input port (default) LVCMOS – 100k PUc (en) AIN5 ADC10 Ch.5 analog input Analog #WAIT Wait cycle request input LVCMOS #ADTRIG ADC10 trigger input LVCMOS Seiko Epson Corporation 1-16 S1C33L26 TECHNICAL MANUAL...
Page 36 39 PA2 I/o I/O port (default) – LVCMOS Type 2 100k PUs Schmitt (dis) SCLK1 i/o FSIO Ch.1 clock input/output (see Table 1.3.2.10.) FPDAT18 o LCD data output FPDAT22 o LCD data output Seiko Epson Corporation 1-17 S1C33L26 TECHNICAL MANUAL...
Page 37 I/O port DST2 DST2 signal output for debugging (default) LVCMOS Type 2 100k PUc Schmitt (dis) i/o I/O port DST1 DST1 signal output for debugging (default) i/o I/O port FPDAT14 o LCD data output Seiko Epson Corporation 1-18 S1C33L26 TECHNICAL MANUAL...
Page 38 Note: In I C mode, both the USIL_DI and USIL_CS pins can be configured as I C data input/output pins. However, they can not be used for I C data input/output at the same time. Seiko Epson Corporation 1-19 S1C33L26 TECHNICAL MANUAL...
Page 39 Clock input #SRDY1 Unused (input) Unused (input) Ready signal input Ready signal output 1.3.3 Package TQFP15-128pin Package (Unit: mm) INDEX 0.13 /0.23 0.09 /0.2 0° /10° /0.75 Figure 1. 3.3.1 TQFP15-128pin Package Dimensions Seiko Epson Corporation 1-20 S1C33L26 TECHNICAL MANUAL...
Page 40 1 OVERVIEW TQFP24-144pin Package (Unit: mm) INDEX 0.13 /0.23 0.09 /0.2 0° /8° /0.7 Figure 1. 3.3.2 TQFP24-144pin Package Dimensions Seiko Epson Corporation 1-21 S1C33L26 TECHNICAL MANUAL...
Page 41 – 0.48 – – 0.08 – – – – – – A1 Corner 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Figure 1. 3.3.3 PFBGA12U-180 Package Dimensions Seiko Epson Corporation 1-22 S1C33L26 TECHNICAL MANUAL...
Page 42 This value indicates the thermal resistance of the package when measured under a windless condition, with the sample suspended alone. Note: The thermal resistance of the package varies significantly depending on how it is mounted on the board and whether forcibly air-cooled. Seiko Epson Corporation 1-23 S1C33L26 TECHNICAL MANUAL...
Page 43 The S1C33L26 contains the C33 PE Core as its core processor. The C33 PE (Processor Element) Core is a Seiko Epson original 32-bit RISC-type core processor for the S1C33 Family microprocessors. Based on the C33 STD Core CPU features, some useful C33 ADV Core functions/instruc- tions were added and some of the infrequently used ones in general applications are removed to realize a high cost- performance core unit with high processing speed.
Page 44 Branch condition: Z | N ^ V Delayed branching possible jrle.d jrugt sign8 PC relative conditional jump Branch condition: !Z & !C Delayed branching possible jrugt.d jruge sign8 PC relative conditional jump Branch condition: !C Delayed branching possible jruge.d Seiko Epson Corporation S1C33L26 TECHNICAL MANUAL...
Page 45 Invert a specified bit in memory data bnot [%rb],imm3 Other Bytewise swap on byte boundary in word swap %rd,%rs pushn Push general-purpose registers %rs–%r0 onto the stack popn Pop data for general-purpose registers %rd–%r0 off the stack Seiko Epson Corporation S1C33L26 TECHNICAL MANUAL...
Page 46 Bytewise swap on halfword boundary in word push Push single general-purpose register Pop single general-purpose register Push special registers %ss–ALR onto the stack pushs pops Pop data for special registers %sd–ALR off the stack Seiko Epson Corporation S1C33L26 TECHNICAL MANUAL...
Page 47 (2) Saves the contents of the PC and R0, in that order, to the addresses specified below. PC → 0x60008 R0 → 0x6000c (3) Loads the debug exception vector located at the address 0x00060000 to PC and branches to the debug excep- tion handler routine. Seiko Epson Corporation S1C33L26 TECHNICAL MANUAL...
Page 48 R0 and the PC. Neither hardware interrupts nor NMI interrupts are accepted during a debug exception. Chip ID The S1C33L26 has chip ID bits shown below that allow the application software to identify CPU type, model, and chip version. Core ID Bits (D[7:0]/0x20008) These bits provide an 8-bit ID code that indicates the chip core type.
Page 49 3 MEMORY MAP Memory Map Figure 3.1 shows a memory map of the entire S1C33L26 address space. Figure 3.2 shows a memory map of the embedded memory and the internal I/O area. Internal Areas External Areas Area 22 0xffff ffff...
Page 50 The following describes the area configuration of the S1C33L26. Boot Address When the S1C33L26 is powered on or reset, the system boots up from a NOR Flash/external ROM, SPI-EEPROM, or a PC connected via RS232C interface specified using the BOOT and #CE10 pins.
Page 51 DSTRAM cannot be accessed from the CPU and DMAC. For more information on the look-up table and memory switching, see the “LCD Controller (LCDC)” chapter. Note: When DSTRAM is switched to LUTRAM, locate the DMAC control table in IVRAM (Area 3) or an external RAM. Seiko Epson Corporation S1C33L26 TECHNICAL MANUAL...
Page 52 SRAMC and/or SDRAMC according to the devices connected. Although the internal address and internal data buses of the S1C33L26 are both 32 bits wide, the maximum external data bus width is 16 bits (D[15:0]) and the maximum external address bus width is 26 bits (A[25:0]) due to the limited number of pins available.
Page 53 SRAMC register. The S1C33L26 is designed under the assumption that the CPU is set in HALT status and the LCDC only is ac- tive while the SDRAM is placed into self-refresh mode.
Page 54 H + 1 15 (*1) 2 (*2) W + 1 H + 1 W + 1 H + 1 16 (*1) 1 (*2) W + 1 H + 1 W + 1 H + 1 Seiko Epson Corporation S1C33L26 TECHNICAL MANUAL...
Page 55 *3: When the LCDC loads display data stored in an external SDRAM (VRAM) to the FIFO Note that the factor when the LCDC accesses the external SDRAM across the boundary between the main and sub-window areas (located in the same SDRAM) are not taken into consideration. Seiko Epson Corporation S1C33L26 TECHNICAL MANUAL...
Page 56 4 POWER SUPPLY Power Supply This section explains the operating voltage of the S1C33L26. Power Supply Pins The S1C33L26 has the power supply pins shown in Table 4.1.1. Table 4. 1.1 Power Supply Pins Pin No. Pin name Description TQFP15...
Page 57 RAM (BBRAM). I/O Interface Voltage (HV The HV voltage is used for interfacing with external I/O signals. For the output interface of the S1C33L26, the voltage is used as high level and the V voltage as low level. The V...
Page 58 (2) Abnormal noise must not be applied to the device. (3) The potential at the unused input should be fixed at LV , HV , AV , or V (4) No outputs should be shorted. Seiko Epson Corporation S1C33L26 TECHNICAL MANUAL...
Page 59 OSC3 clock cycles to ensure that the chip is reset. Also the internal reset signal is negated when the default OSC3 oscillation stabilization wait time has elapsed after the #RESET pin goes high. The S1C33L26 is reset by the low state (= 0) on the internal reset signal, and starts operating when the reset signal goes high (= 1).
Page 60 (See the “Pin Functions” section in the “Overview” chapter.) Other internal peripheral – Initialized or undefined (See each I/O map.) circuits Note: The S1C33L26 does not support a hot reset feature that maintains I/O pin status and the TTBR value. Seiko Epson Corporation S1C33L26 TECHNICAL MANUAL...
Page 61 For the specific initial settings done on the peripheral circuits after an initial reset, see each I/O map or circuit descriptions. NMI Input The S1C33L26 has two NMI sources that generate NMI. (1) #NMI pin (external input) (2) Watchdog timer (software selectable) Figure 5.2.1 shows the configuration of the NMI circuit.
Page 62 NMI by the Watchdog Timer The S1C33L26 has a built-in watchdog timer to detect runaway of the CPU. The watchdog timer outputs a signal if it is not reset with software (due to CPU runaway) in the programmed cycles. The output signal can generate either NMI or reset.
Page 63 0x96 to CMUP[7:0]/CMU_PROTECT register. Note that since unnecessary rewrites to the CMU control registers could lead to erratic system operation, CMUP[7:0] should be set to other than 0x96 unless the CMU control registers must be rewritten. Seiko Epson Corporation S1C33L26 TECHNICAL MANUAL...
Page 64 • Before using a ceramic resonator, please be sure to contact Murata Manufacturing Co., Ltd. for further infor- mation on conditions of use for ceramic resonators. For details of oscillation characteristics and external clock input characteristics, see “Electrical Characteristics.” Seiko Epson Corporation S1C33L26 TECHNICAL MANUAL...
Page 65 OSC1 Oscillator Circuit The S1C33L26 contains an oscillator circuit (OSC1) used to generate a 32.768 kHz (typ.) clock as the clock source for timekeeping operation of the RTC. The OSC1 clock can also be used as a power-saving operating clock for the core system or peripheral circuits.
Page 66 (see “Electric Characteristics”). After the PLL clock is stabilized, the clock source for the system can be switched over to the PLL. • Be sure to turn the PLL off before setting the CPU into SLEEP mode (before executing the slp instruction). Seiko Epson Corporation S1C33L26 TECHNICAL MANUAL...
Page 67 CMU_PLLCTL0 register = 0) and the clock source is other than the PLL (CLKSEL[1:0]/CMU_ OSCSEL register is not 0x2). If the frequency multiplication rate is changed while the system is operating with the PLL clock, the system may operate erratically. Seiko Epson Corporation S1C33L26 TECHNICAL MANUAL...
Page 68 60 MHz 1/1 (0x0) x3 (0x2) 40 MHz 1/1 (0x0) x2 (0x1) 36 MHz 72 MHz 1/1 (0x0) x2 (0x1) 48 MHz 72 MHz 1/8 (0x7) x12 (0xb) 60 MHz 1/8 (0x7) x10 (0x9) Seiko Epson Corporation S1C33L26 TECHNICAL MANUAL...
Page 69 The SSCG can be turned on or off using SSMCON/CMU_SSCG0 register. Setting SSMCON to 1 causes the SSCG to start operating. When initially reset, SSMCON is initialized to 0, with the SSCG turned off (bypassed). Seiko Epson Corporation S1C33L26 TECHNICAL MANUAL...
Page 70 • When the PLL is off, the initial values and the written values cannot be read correctly from SSMCIDT[3:0] and SSMCITM[3:0] since the source clock is not supplied from the PLL (different values are read out). The correct values can be read out when the PLL is on. Seiko Epson Corporation S1C33L26 TECHNICAL MANUAL...
Page 71 Switching the system clock to PLL from OSC1 1. Switch the system clock to OSC3 from OSC1 by following the procedure shown above. 2. Switch the system clock to PLL from OSC3 by following the procedure shown above. Seiko Epson Corporation S1C33L26 TECHNICAL MANUAL...
Page 72 SYSCLK/2 (SYSCLK is used for the SDRAM clock). MCLK can be selected at any time. However, up to 2 clock cycles are required before the clocks are actually changed after altering the register values. Seiko Epson Corporation 6-10 S1C33L26 TECHNICAL MANUAL...
Page 73 To supply BCLK in HALT mode, set BCLK_EN to 1 (default). The modules listed above operates even in HALT mode. BCLK stops in SLEEP mode (when the slp instruction is executed) regardless of the BCLK_EN set value. Seiko Epson Corporation 6-11 S1C33L26 TECHNICAL MANUAL...
Page 74 GCLK is supplied even in HALT mode when GCLK_EN is set to 1. To stop the GE module in HALT mode, set GCLK_EN to 0 before executing the halt instruction. In SLEEP mode (when the slp instruction is executed), GCLK stops even if GCLK_EN is set to 1. Seiko Epson Corporation 6-12 S1C33L26 TECHNICAL MANUAL...
Page 75 : SDCLK = 1 : 2), the SDRAMC operates with SDCLK (Max. 72 MHz) configured to double the frequency of MCLK (Max. 36 MHz), while the SRAMC operates on the same frequency as MCLK. Seiko Epson Corporation 6-13 S1C33L26 TECHNICAL MANUAL...
Page 76 CMU_CLK can be selected at any time. However, switching over the clocks creates hazards. Note: Settings other than those listed in Table 6.8.1 are reserved for testing. Do not set undescribed val- ues to CMU_CLKSEL[4:0] as undesired clocks may output. Seiko Epson Corporation 6-14 S1C33L26 TECHNICAL MANUAL...
Page 77 6 CLOCK MANAGEMENT UNIT (CMU) Standby Modes The S1C33L26 supports two standby modes: HALT and SLEEP. Power consumption on the chip can be greatly re- duced by placing the CPU in one of these standby modes. 6.9.1 HALT Mode The CPU suspends program execution upon executing the halt instruction and enters HALT mode. HALT mode is effective in reducing power consumption on the chip when running the CPU is unnecessary, such as when waiting for external input or responses from peripheral circuits.
Page 78 (Default: 0x0) Note: Do not select the system clock from deactivated clock sources. It will cause the system to hang as the CMU does not include a protection mechanism against such system clock selection. Seiko Epson Corporation 6-16 S1C33L26 TECHNICAL MANUAL...
Page 79 Example: When OSC3 oscillation start time (max.) = 10 ms and f = 48 MHz SYSCLK OSC3 oscillation stabilization wait time ≥ 480,000 [cycles] OSC3WT[3:0] should be set to 0x3 (OSC3 oscillation stabilization wait time = 524,288 cycles). Seiko Epson Corporation 6-17 S1C33L26 TECHNICAL MANUAL...
Page 80 Frame rate = ————— [Hz] HT × VT : LCLK frequency LCLK Horizontal total period (horizontal panel size + horizontal non-display period) [pixels] Vertical total period (vertical panel size + vertical non-display period) [lines] Seiko Epson Corporation 6-18 S1C33L26 TECHNICAL MANUAL...
Page 81 The USBCLK_EN default setting is 0, which stops the clock supply. Setting USBCLK_EN to 1 sup- plies USBCLK to the USB function controller. If no USB operation is required, stop the clock supply to reduce current consumption. Seiko Epson Corporation 6-19 S1C33L26 TECHNICAL MANUAL...
Page 82 The PCLK2_EN default setting is 1, which enables the clock supply. If all the modules listed above can be stopped, disable the clock supply by setting PCLK2_EN to 0 to reduce current consumption. Seiko Epson Corporation 6-20 S1C33L26 TECHNICAL MANUAL...
Page 83 1 (R/W): SYSCLK/2 0 (R/W): SYSCLK/1 (default) MCLK is the main system clock for S1C33L26. This bit selects either SYSCLK (selected with SYS- CLKDIV[2:0]) or its halved clock. When using the SDRAMC in double frequency mode (MCLK : SDCLK = 1 : 2), MCLK should be set to SYSCLK/2 (SYSCLK is used for the SDRAM clock).
Page 84 CMU_CLK can be selected at any time. However, switching over the clocks creates hazards. Note: Settings other than those listed in Table 6.10.6 are reserved for testing. Do not set unde- scribed values to CMU_CLKSEL[4:0] as undesired clocks may output. Seiko Epson Corporation 6-22 S1C33L26 TECHNICAL MANUAL...
Page 85 OSCSEL register is not 0x2). If the PLL input clock is changed while the system is operating with the PLL clock, the system may operate erratically. • For the range of the input clock frequency, see “Electrical Characteristics.” Seiko Epson Corporation 6-23 S1C33L26 TECHNICAL MANUAL...
Page 86 “Electrical Characteristics.” D[3:2] PLLV[1:0]: PLL V-Divider Setup Bits frequency obtained by <Output clock frequency × W> falls within the Sets the W value so that the f range of 100 to 400 MHz. Seiko Epson Corporation 6-24 S1C33L26 TECHNICAL MANUAL...
Page 87 Sets the LPF resistance value of the PLL (RS value) according to the input clock (OSC3) frequency. Table 6. 10.11 RS Value Settings PLLRS[3:0] [MHz] REFCK 5 ≤ f < 20 REFCK 20 ≤ f ≤ 150 REFCK Other Setting prohibited (Default: 0x8) Seiko Epson Corporation 6-25 S1C33L26 TECHNICAL MANUAL...
Page 88 Always set these bits to 0x1. (Default: undefined) D[3:0] SSMCIDT[3:0]: SSCG Maximum Frequency Change Width Setting Bits Sets the maximum frequency change width in SS modulation of the SSCG. (See Section 6.5, “SSCG.”) Seiko Epson Corporation 6-26 S1C33L26 TECHNICAL MANUAL...
Page 89 0x96. When rewriting the CMU control registers has finished, CMUP[7:0] should be set to other than 0x96 to prevent accidental writing to the CMU registers. Seiko Epson Corporation 6-27 S1C33L26 TECHNICAL MANUAL...
Page 90 Prescaler (PSC) PSC Module Overview The S1C33L26 incorporates a prescaler (PSC) module to generate clocks for timer and serial interface operations. The PSC module consists of two frequency dividers (PSC Ch.0 and PSC Ch.1) that generate 15 different frequen- cies by dividing the PCLK1 and PCLK2 clock supplied from the clock management unit (CMU) into 1/1 to 1/16K.
Page 91 • 8-bit programmable timer (T8) Ch.1 • 8-bit programmable timer (T8) Ch.3 (clock source for USIL) • 8-bit programmable timer (T8) Ch.5 • 8-bit programmable timer (T8) Ch.7 • Remote controller (REMC) • I/O ports (GPIO) Seiko Epson Corporation S1C33L26 TECHNICAL MANUAL...
Page 92 Real-Time Clock (RTC) RTC Module Overview The S1C33L26 incorporates a real-time clock (RTC) with a perpetual calendar, and an OSC1 oscillator circuit to generate the operating clock for the RTC. The RTC and OSC1 oscillator circuit operate in SLEEP mode. Moreover, the RTC can periodically generate inter- rupt requests to the CPU.
Page 93 The number of days in each month and leap years are taken into account, so that when months change the counter is reset to 0 along with the 1-day counter, and outputs a carry over of 1 to the 1-month counter. The count data is read out and written using RTCDH[1:0]/RTC_DAY register. Seiko Epson Corporation S1C33L26 TECHNICAL MANUAL...
Page 94 2399. Years (0 to 99) without a remainder when divided by 4 are considered leap years. When the 1-year and 10-year counters both are 0, a common year is assumed. Seiko Epson Corporation S1C33L26 TECHNICAL MANUAL...
Page 95 2 cycles 1 cycle 0 cycles (cannot be set) (Default: 0x7) The S1C33L26 is able to operate with RTCWT[2:0] ≥ 1. 8.3.2 RTC Initial Sequence Immediately after power-on, the contents of RTC registers are indeterminate. After powering on, follow the proce- dure below to let the RTC start ticking the time.
Page 96 RTCRST/RTC_CNTL0 register is the software reset bit used to reset the items shown below. • Divider (32 kHz to 2 Hz bits) • Interrupt request signal • WAKEUP signal • Some register bits (see Section 8.6 for the control bits and their initial values.) Seiko Epson Corporation S1C33L26 TECHNICAL MANUAL...
Page 97 RTCBSY read RTCBSY read 4 ms wait RTCBSY = 0? RTCBSY = 0? Register write Register write RTCHLD ← 0 RTCHLD ← 0 Figure 8. 3.5.1 Procedure for Checking whether the RTC is Busy Seiko Epson Corporation S1C33L26 TECHNICAL MANUAL...
Page 98 While RTCRDHLD is set to 1, the buffered data is read out from the counter registers. Be sure to reset RTCRD- HLD to 0 after the buffered data is read out. This operation does not affect the counters. The counters keeps count- ing while RTCRDHLD is set to 1. Seiko Epson Corporation S1C33L26 TECHNICAL MANUAL...
Page 99 RTCT[2:0] should be set while RTC interrupts are disabled. (See the procedure for enabling and disabling inter- rupts described below.) Setting interrupt conditions The RTC of the S1C33L26 supports level-sensed interrupt only. Enabling and disabling interrupts The RTC interrupt requests output to the ITC are enabled by setting RTCIEN/RTC_INTMODE register to 1 and disabled by setting it to 0.
Page 100 When a software reset is performed (RTCRST → 1 → 0), RTCIRQ and RTCIEN are reset to 0 to disable the interrupt request output. Also RTCT[2:0] is reset to 0x1. WAKEUP and #STBY Pins The S1C33L26 has a battery backup function that allows the system to turn the system power (LV , PLLV , AV...
Page 101 Power On using the POWER SW (1) Press the POWER SW. The switch must be held down until Step (5) has completed. (2) The regulator is enabled to output voltage and the 1.8 V (and 3.3 V) voltage is supplied to the S1C33L26 , PLLV...
Page 102 Power On using an RTC interrupt (1) When an RTC interrupt occurs, the WAKEUP output level goes 1 (high). (2) The regulator is enabled to output voltage and the 1.8 V (and 3.3 V) voltage is supplied to the S1C33L26 , PLLV...
Page 103 RTCIMD: Reserved (Always be sure to set to 1.) RTCIEN: RTC Interrupt Enable Bit This bit enables or disables RTC interrupt request output to the ITC. 1 (R/W): Enable interrupts 0 (R/W): Disable interrupts (software reset value) Seiko Epson Corporation 8-12 S1C33L26 TECHNICAL MANUAL...
Page 104 This bit starts or stops the divider. It also indicates divider operating status. 1 (W): Stops divider 0 (W): Starts divider 1 (R): Divider/counters are idle 0 (R): Divider/counters are operating (software reset value) Seiko Epson Corporation 8-13 S1C33L26 TECHNICAL MANUAL...
Page 105 1 second and no correction is conducted on the carry encountered in the second time and on. In this case, the timekeeping data gets out of order. Therefore, be sure to reset RTCHLD to 0 as soon as pos- sible after completing the required write operation. Seiko Epson Corporation 8-14 S1C33L26 TECHNICAL MANUAL...
Page 106 The counter counts from 0 to 9 with a carry over of 1 from the 10-second counter. This counter is reset to 0 after 9 and outputs a carry over of 1 to the 10-minute counter. Seiko Epson Corporation 8-15 S1C33L26 TECHNICAL MANUAL...
Page 107 3 with a carry over of 1 from the 1-day counter. The number of days in each month and leap years are taken into account, so that when months change the counter is reset to 0 along with the 1-day counter, and a carry over of 1 is output to the 1-month counter. Seiko Epson Corporation 8-16 S1C33L26 TECHNICAL MANUAL...
Page 108 The counter counts from 0 to 9 with a carry over of 1 from the month counter. This counter is reset to 0 after 9 and outputs a carry over of 1 to the 10-year counter. Seiko Epson Corporation 8-17 S1C33L26 TECHNICAL MANUAL...
Page 109 RTC interrupt occurs. WUP_POL: WAKEUP Polarity Select Bit This bit selects the active level of the WAKEUP output signal. 1 (R/W): Active low 0 (R/W): Active high (software reset value) Seiko Epson Corporation 8-18 S1C33L26 TECHNICAL MANUAL...
Page 110 9 SRAM CONTROLLER (SRAMC) SRAM Controller (SRAMC) The S1C33L26 includes a bus controller that controls access to external memories. The bus controller consists of an SRAM controller (SRAMC) for controlling the SRAM, an SDRAM controller (SDRAMC) for controlling the SDRAM, and a data queue buffer (DQB) for efficiently reading from external memories.
Page 111 *2 Since the address bus is 26-bit wide, valid area for each area is 64M bytes from the top. Figure 9. 4.1 S1C33L26 External Memory Space Areas 4, 5, 7 to 10, 13 to 16, and 19 to 22 comprise an external memory area accessible from the SRAMC, to which external memory devices may be connected.
Page 112 Note: Letter ‘x’ in the control bit and #CE names denotes a #CE area number (4, 5, or 7 to 10). Endian mode The S1C33L26 supports little endian mode only. Device type The device size can be selected from 8 bits and 16 bits. Additionally, for a 16-bit device, the device type can also be selected from the A0 (default) or BSL modes.
Page 113 #CE hold cycle via #WAIT BCLK valid A[25:0] #CEx #RD/#WR* valid D[15:0] (RD) valid D[15:0] (WR) #WAIT (CExSETUP = 0x0) (CExWAIT = 0x1) (CExHOLD = 0x0) Figure 9. 4.2.1 Example of Timing Parameter Settings Seiko Epson Corporation S1C33L26 TECHNICAL MANUAL...
Page 114 9.5.2 Data Configuration in Memory The S1C33L26 SRAMC handles byte (8-bit), halfword (16-bit), and word (internal 32-bit) data. To access data in a memory, addresses aligned to the boundary of the data size must be specified. Specifying other addresses generates address misaligned exceptions.
Page 115 External Bus Operation The internal data bus size in the S1C33L26 is 32 bits. Note, however, that it has 16 external bus pins D[15:0]. Depending on the device size and data size of the instruction executed, two or more bus operations may occur.
Page 116 A[25:0] #CEx valid D[15:0] #WAIT Figure 9. 6.1.1 SRAM Read Timing with No Static Wait Cycle valid A[25:0] #CEx #WR* valid D[15:0] #WAIT Figure 9. 6.1.2 SRAM Write Timing with No Static Wait Cycle Seiko Epson Corporation S1C33L26 TECHNICAL MANUAL...
Page 117 #CEx valid D[15:0] #WAIT Figure 9. 6.1.3 SRAM Read Timing with Static Wait Cycle Static wait cycle valid A[25:0] #CEx #WR* valid D[15:0] #WAIT Figure 9. 6.1.4 SRAM Write Timing with Static Wait Cycle Seiko Epson Corporation S1C33L26 TECHNICAL MANUAL...
Page 118 Wait cycle valid A[25:0] #CEx valid D[15:0] #WAIT Figure 9. 6.2.1 SRAM Read Timing with External #WAIT Wait cycle valid A[25:0] #CEx #WR* valid D[15:0] #WAIT Figure 9. 6.2.2 SRAM Write Timing with External #WAIT Seiko Epson Corporation S1C33L26 TECHNICAL MANUAL...
Page 119 4 cycles 1 cycle D11–8 CE5WAIT #CE5 static wait cycle CE5WAIT[3:0] Wait cycle [3:0] 15 cycles 0 cycles D7–6 CE4SETUP #CE4 setup cycle CE4SETUP[1:0] Setup cycle 0x3 R/W [1:0] 4 cycles 1 cycle Seiko Epson Corporation 9-10 S1C33L26 TECHNICAL MANUAL...
Page 120 Configures the #CEx signal setup time (#CEx falling edge to read/write signal falling edge). Table 9. 7.2 #CE Setup Time Settings CExSETUP[1:0] Setup time 4 cycles 3 cycles 2 cycles 1 cycle (Default: 0x3) Seiko Epson Corporation 9-11 S1C33L26 TECHNICAL MANUAL...
Page 121 #CE hold cycle via #WAIT BCLK valid A[25:0] #CEx #RD/#WR* valid D[15:0] (RD) valid D[15:0] (WR) #WAIT (CExSETUP = 0x0) (CExWAIT = 0x1) (CExHOLD = 0x0) Figure 9. 7.1 Example of Timing Parameter Settings Seiko Epson Corporation 9-12 S1C33L26 TECHNICAL MANUAL...
Page 122 Pins to be used 0x3–0x2 8-bit device A[25:0], D[7:0], #CEx, #RD, #WRL 16-bit BSL device A[25:1], D[15:0], #CEx, #RD, #WRL, #BSL(A0), #BSH 16-bit A0 device A[25:1], D[15:0], #CEx, #RD, #WRL, #WRH (Default: 0x0) Seiko Epson Corporation 9-13 S1C33L26 TECHNICAL MANUAL...
Page 123 10 SDRAM CONTROLLER (SDRAMC) SDRAM Controller (SDRAMC) The S1C33L26 includes a bus controller that controls access to external memories. The bus controller consists of an SRAM controller (SRAMC) for controlling the SRAM, an SDRAM controller (SDRAMC) for controlling the SDRAM, and a data queue buffer (DQB) for efficiently reading from external memories.
Page 124 Note: Setting SDON to 1 overrides the external SRAM access conditions for the #CE7 area set in the SRAMC. 10.4.2 SDRAM Size and Access Condition Settings Table 10.4.2.1 lists the conditions related to SDRAM size and timing parameters that the SDRAMC can accommo- date. Seiko Epson Corporation 10-2 S1C33L26 TECHNICAL MANUAL...
Page 125 – – – When reading/writing byte data, the SDRAMC decodes A0/#BSL and #WRH/#BSH into DQML and DQMH. Upper address bits that are not used (depending on memory size) are all fixed to 0. Seiko Epson Corporation 10-3 S1C33L26 TECHNICAL MANUAL...
Page 126 #SDWE DQMH DQMU DQMH DQML DQML DQML BA[1:0] 8M × 16 bits (4 banks) A[11:0] DQ[7:0] #RAS #CAS 8M × 8 bits (4 banks) × 2 Figure 10. 4.2.2 16MB SDRAM Connection Example Seiko Epson Corporation 10-4 S1C33L26 TECHNICAL MANUAL...
Page 127 : ACTIVE to ACTIVE command cycle time : Auto-refresh cycle time : Self-refresh end to ACTIVE command period These timing parameters can be set from 1 to 16 cycles in SDCLK using T80NS[3:0]/SDRAMC_CFG reg- ister. Seiko Epson Corporation 10-5 S1C33L26 TECHNICAL MANUAL...
Page 128 These timing parameters can be set from 1 to 4 cycles in SDCLK using T24NS[1:0]/SDRAMC_CFG regis- ter. Table 10. 4.2.6 and t Settings T24NS[1:0] 4 cycles 3 cycles 2 cycles 1 cycle (Default: 0x0) Seiko Epson Corporation 10-6 S1C33L26 TECHNICAL MANUAL...
Page 129: Sdramc_App Register
Write 0x14 to the SDRAMC_INIT register to set INIMRS to 1. Then write any data to a specific address of SDRAM shown below according to the CAS latency (MRS) or extended mode parameters (EMRS). Seiko Epson Corporation 10-7 S1C33L26 TECHNICAL MANUAL...
Page 130: Sdramc_App Register
#SDRAS #SDCAS #SDWE DQMH/DQML SDON bit INIPRE bit INIREF bit INIMRS bit INIDO bit SDA10 Valid Valid SDBA[1:0] Valid SDA[12:11, 9:0] Valid Valid 100 µs (min.) Figure 10. 5.1.1 SDRAM Power-on and Initialization Seiko Epson Corporation 10-8 S1C33L26 TECHNICAL MANUAL...
Page 131 SDRAM Bus Operations The external data bus of the S1C33L26 is sized to 16 bits. Depending on the device size and data size of the instruc- tion executed, two or more bus operations may occur. The table below shows bus operations in the SDRAM area.
Page 132 READ ACTV NOP READ SDCKE #SDCS #SDRAS #SDCAS #SDWE SDBA[1:0] SDA10 ROW1 ROW2 SDA[12:11, 9:0] ROW1 COLn ROW2 COL0 DQMH/DQML DQ[15:0] (n+1) latency latency Figure 10. 5.4.2 Changing Row Address During Burst Read Seiko Epson Corporation 10-10 S1C33L26 TECHNICAL MANUAL...
Page 133 SDA[12:11, 9:0] ROW1 ROW2 COLn COLm ROW3 COLl DQMH/DQML DQ[15:0] (n+1) (m+1) Bank 1 Active Read Precharge Bank 2 Active Read latency (Bank 1 cannot be accessed.) Figure 10. 5.4.4 Bank Interleaved Access Seiko Epson Corporation 10-11 S1C33L26 TECHNICAL MANUAL...
Page 134: Sdramc: Sdram Refresh
Therefore, set a value equal to or less than 299 (0x12b) to AURCO[11:0]. SDCLK Command PALL NOP ACTV SDCKE #SDCS #SDRAS #SDCAS #SDWE SDBA[1:0] SDA10 SDA[12:11, 9:0] DQMH/DQML DQ[15:0] Figure 10. 5.5.1 Auto-Refresh Seiko Epson Corporation 10-12 S1C33L26 TECHNICAL MANUAL...
Page 135 Note that auto-refresh mode cannot be canceled. Note: Be sure to avoid setting SDON/SDRAMC_INIT register to 0 (SDRAMC disabled) during self- refreshing. Before disabling the SDRAMC, always make sure the SDRAMC is not in self-refresh mode. Seiko Epson Corporation 10-13 S1C33L26 TECHNICAL MANUAL...
Page 136 6. Set SDON/SDRAMC_INIT register to 1 to enable the SDRAMC. 7. Initialize the SDRAMC. 10.6 Data Queue Buffer (DQB) The bus controller of the S1C33L26 also includes a data queue buffer (DQB) to increase the C33 PE Core memory access performance. Data queue Data input...
Page 137 INIDO is set to 1 when the initialization sequence is completed. Make sure that INIDO is set to 1 be- fore the SDRAM is accessed. INIMRS: MRS Command Enable for Initialization Bit Enables to output the MRS (Mode Register Set) command for initializing the SDRAM. 1 (R/W): Enabled 0 (R/W): Disabled (default) Seiko Epson Corporation 10-15 S1C33L26 TECHNICAL MANUAL...
Page 138 • After the initial sequence commands are executed, the command enable bit must be set to 0. Write 0x10 to the SDRAMC_INIT register after the last initialization command has been executed. • The self-refresh function must be disabled until the SDRAM has finished initialization. Seiko Epson Corporation 10-16 S1C33L26 TECHNICAL MANUAL...
Page 139 , and t Cycles Bits Sets the t and t SDRAM timing parameters. • t ACTIVE to ACTIVE command cycle time • t Auto-refresh cycle time • t Self-refresh end to ACTIVE command period Seiko Epson Corporation 10-17 S1C33L26 TECHNICAL MANUAL...
Page 140 SREFDO is set to 0 while the SDRAM is placed into self-refresh mode. Otherwise, SREFDO is set to 1. Before entering the SLEEP mode, always be sure to read this bit using a program stored elsewhere (i.e., not in the SDRAM) to confirm that the SDRAM is in self-refresh mode. Seiko Epson Corporation 10-18 S1C33L26 TECHNICAL MANUAL...
Page 141 RFP: Maximum refresh period [s] ROWS: Row address size SDCLK clock frequency [Hz] Burst length (= 2) CAS latency PRECHARGE command period [Number of cycles] ACTIVE to READ/WRITE delay time [Number of cycles] Seiko Epson Corporation 10-19 S1C33L26 TECHNICAL MANUAL...
Page 142 SDRAM operation in uncontrolled status. The following operations stop the SDCLK. Do not per- form these operations when the SDRAM may be accessed. - Placing the S1C33L26 into SLEEP status - Disabling the clock supply to the SDRAMC module Besides from the CPU, the SDRAM can be accessed from the DMAC (if DMA transfers are enabled toward the SDRAM).
Page 143 11.1 CCU Module Overview In order to enable fast access to instructions and data, the S1C33L26 incorporates a cache controller (CCU) that runs by the 4-Way set associative method. Addresses 0x1f800 to 0x1fbff (1K bytes) and 0x1fc00 to 0x1ffff (1K...
Page 144 Configured with 4-Ways, the CCU has four frames of data assigned the same entry number. If nothing is hit, it is needed to select one of the four Ways to replace with, in which case, the LRU section stores the Way number. Seiko Epson Corporation 11-2 S1C33L26 TECHNICAL MANUAL...
Page 145: Ccu: Selecting Area To Be Cached
Among addresses output by the SRAMC, two bits at A[7:6] represent the entry number (frame offset). A[25:8] is deemed as a comparison address and compared with the address for comparison (CA[25:8]) stored in the TAG sec- tion containing four Ways under the entry selected in A[7:6]. Seiko Epson Corporation 11-3 S1C33L26 TECHNICAL MANUAL...
Page 146 LRU information. The line cached is enabled in the CCU, after which instructions/data in the same line are read from the cache memory. Other lines within the same frame are disabled until it is refilled through access to the relevant addresses. Seiko Epson Corporation 11-4 S1C33L26 TECHNICAL MANUAL...
Page 147 (when not hit to the cached data). Executing the reti instruction at the end of the interrupt handler routine reset IL[2:0] to 0 and releases the cache lock status. Seiko Epson Corporation 11-5 S1C33L26 TECHNICAL MANUAL...
Page 148 0 Disable Instruction cache enable 1 Enable 0 Disable Data cache enable 1 Enable 0 Disable D[31:9] Reserved WBEN: Write Buffer Enable Bit Enables the write buffer. 1 (R/W): Enabled (default) 0 (R/W): Disabled Seiko Epson Corporation 11-6 S1C33L26 TECHNICAL MANUAL...
Page 149 0 when being read. D2–0 ARDC[2:0] Data cache area select ARDC[2:0] Area 0x0 R/W Area 22 Area 21 Area 20 Area 19 Area 18 Area 17 Areas 15 & 16 Area 14 D[31:7] Reserved Seiko Epson Corporation 11-7 S1C33L26 TECHNICAL MANUAL...
Page 150 1 Locked 0 Not locked (CCU_STAT) DCLKS Data cache lock status 1 Locked 0 Not locked Instruction cache operating status 1 Active 0 Inactive Data cache operating status 1 Active 0 Inactive D[31:4] Reserved Seiko Epson Corporation 11-8 S1C33L26 TECHNICAL MANUAL...
Page 151 1 upon completion of writing to the external memo- WBEMPTY: Write Buffer Empty Flag Bit Indicates the write buffer status. 1 (R): Empty (default) 0 (R): Full Seiko Epson Corporation 11-9 S1C33L26 TECHNICAL MANUAL...
Page 152 C33 PE Core and CCU using the slowest possible clock speed. Table 11. 7.4 CCLK Division Ratio Selection CLK_DOWN[1:0] Division ratio (Default: 0x0) For more information on CCLK, see the “Clock Management Unit (CMU)” chapter. Seiko Epson Corporation 11-10 S1C33L26 TECHNICAL MANUAL...
Page 153 Interrupt enable level Vector number Peripheral module Interrupt Interrupt flag Cause of interrupt 1 request Interrupt enable Interrupt level Interrupt flag Cause of interrupt n Vector number Interrupt enable Figure 12. 1.1 Interrupt System Seiko Epson Corporation 12-1 S1C33L26 TECHNICAL MANUAL...
Page 154 The vector table contains the vectors to the interrupt handler routines (handler routine start address) that will be read by the C33 PE Core to execute the handler when an interrupt occurs. Table 12.2.1 shows the vector table of the S1C33L26. Table 12.
Page 155 Vector table base address The S1C33L26 allows the base (starting) address of the vector table to be set using the TTBR register. “TTBR” indicated in Table 12.2.1 means the value that is set to this register. Set the TTBR register in the initial routine executed after booting.
Page 156 If multiple maskable interrupt causes occur simultaneously, the interrupt cause with the highest interrupt level and lowest vector number becomes the subject of the interrupt request to the C33 PE Core. Interrupts with lower levels are held until the above conditions are subsequently met. Seiko Epson Corporation 12-4 S1C33L26 TECHNICAL MANUAL...
Page 157 12.4 In the S1C33L26, a low level input to the #NMI pin or the watchdog timer can generate a non-maskable interrupt (NMI). The vector number for NMI is 7, with the vector address set to the vector table's starting address + 28 bytes.
Page 158 The immediately preceding interrupt is held. Note: Make sure that the PSR IE bit is set to 0 before setting the interrupt level registers (ITC_xxx_LV). Seiko Epson Corporation 12-6 S1C33L26 TECHNICAL MANUAL...
Page 159 13.1 DMAC Module Overview The S1C33L26 incorporates a DMA controller (DMAC) capable of controlling eight table DMA channels. The table DMA transfers data according to the control information programmed in the RAM. The following shows the features of the DMAC.
Page 160 Ch.2: Base + 0x40 0xfff 4,095 Ch.3: Base + 0x60 Ch.4: Base + 0x80 Ch.5: Base + 0xa0 4,096 Ch.6: Base + 0xc0 Ch.7: Base + 0xe0 Source type 1 Pointer 0 Data Seiko Epson Corporation 13-2 S1C33L26 TECHNICAL MANUAL...
Page 161 (Same contents as 4th word) Ch.1: Base + 0x3c [31:0] (32 bits) Ch.2: Base + 0x5c Ch.3: Base + 0x7c Ch.4: Base + 0x9c Ch.5: Base + 0xbc Ch.6: Base + 0xdc Ch.7: Base + 0xfc Seiko Epson Corporation 13-3 S1C33L26 TECHNICAL MANUAL...
Page 162 Increment Fixed DSINC[1:0] = 0x0: Address fixed The destination address is not changed by a data transfer performed. Even when transferring multiple data, the transfer data is always written to the same address. Seiko Epson Corporation 13-4 S1C33L26 TECHNICAL MANUAL...
Page 163 DMAC performs a 16-bit read from the specified source address to obtain the pointer. • PTW = 1: 8 bits DMAC performs an 8-bit read from the specified source address to obtain the pointer. Seiko Epson Corporation 13-5 S1C33L26 TECHNICAL MANUAL...
Page 164 DMAC invocation by a cause of interrupt in internal peripheral modules To respective channels of the DMAC, hardware trigger sources (causes of interrupt in peripheral modules) shown in Table 13.4.1 are assigned, which can be selected with the TRG_SELx[1:0]/DMAC_TRG_SEL regis- ter. Seiko Epson Corporation 13-6 S1C33L26 TECHNICAL MANUAL...
Page 165 DMA request when the channel is disabled to transfer Triggers are disabled for a channel with the CHEN bit (D3/1st word) set to 0 (DMA transfer disabled). TRGx for the channel will not be set. Seiko Epson Corporation 13-7 S1C33L26 TECHNICAL MANUAL...
Page 166 (5) The DMAC reads the specified data unit from the source address into a buffer and then write it to the destina- tion address. The transfer status flag (RUNx/DMAC_RUN_STAT register) is set and retains 1 while data is being transferred. Seiko Epson Corporation 13-8 S1C33L26 TECHNICAL MANUAL...
Page 167 Transfer counter - 1 Transfer counter = 0? Not occurred High-priority DMA request Occurred Store control information Store control information Set pause flag DMAC interrupt request Figure 13. 5.2.1 Operation Flow in Successive Transfer Mode Seiko Epson Corporation 13-9 S1C33L26 TECHNICAL MANUAL...
Page 168 If ENDFx is set to 1 while DMAIEx is set to 1 (interrupt enabled), the DMAC module outputs an interrupt re- quest to the ITC. An interrupt is generated if the ITC and C33 PE Core interrupt conditions are satisfied. Seiko Epson Corporation 13-10 S1C33L26 TECHNICAL MANUAL...
Page 169 The size of control information is 4 words (16 bytes) per channel. The area for auto-reloading also re- quires 4 words (16 bytes) per channel. Therefore, a consecutive 256-byte space is needed for the con- trol table in order to support eight channels. Seiko Epson Corporation 13-11 S1C33L26 TECHNICAL MANUAL...
Page 170 1 (R/W): Enabled 0 (R/W): Disabled (default) Setting DMAIEx to 1 enables the output of DMAC Ch.x interrupt requests to the ITC. Interrupts from Ch.x will not be generated if DMAIEx is set to 0. Seiko Epson Corporation 13-12 S1C33L26 TECHNICAL MANUAL...
Page 171 FSIO Ch.1 receive buffer full Reserved Hardware trigger disabled (software trigger only) Ch.3 TRG_SEL3[1:0] 16-bit PWM timer (T16A5) Ch.x compare/capture A * FSIO Ch.0 transmit buffer empty USI transmit buffer empty Hardware trigger disabled (software trigger only) Seiko Epson Corporation 13-13 S1C33L26 TECHNICAL MANUAL...
Page 172 Note that acceptance of the trigger does not start a DMA transfer if CHEN (D3/1st word) in control in- formation is set to 0. If DMAONx/DMAC_CH_EN register is set to 0 (forced termination), TRGx that has been set is cleared and the pending DMA request is canceled. Seiko Epson Corporation 13-14 S1C33L26 TECHNICAL MANUAL...
Page 173 Also this bit reverts to 0 when the transfer is suspended due to a high-priority DMA re- quest. When modifying control information after a data transfer or forced termination, check this bit to ensure that the transfer operation is actually completed. Seiko Epson Corporation 13-15 S1C33L26 TECHNICAL MANUAL...
Page 174 TRGx/DMAC_TRG_FLG register, and processes the channels with their bits set, starting with one with the highest-priority (with the channel with the lowest number). When the DMAC resumes DMA transfers that have been suspended, PAUSEx is cleared. Seiko Epson Corporation 13-16 S1C33L26 TECHNICAL MANUAL...
Page 175 8-bit Timers (T8) 14.1 T8 Module Overview The S1C33L26 incorporates an eight-channel 8-bit timer module (T8). The features of T8 are listed below. • 8-bit presettable down counter with an 8-bit reload data register for setting the preset value • The count clock is selectable from 15 clocks output from the prescaler.
Page 176 (or between underflows). The time determined is used to obtain the specified wait time, the intervals between periodic interrupts or A/D triggers, and the programmable serial interface transfer clock. Seiko Epson Corporation 14-2 S1C33L26 TECHNICAL MANUAL...
Page 177 To restart the count from the initial value, the timer should be reset be- fore writing 1 to PRUN. When the timer is reset during running, the timer loads the reload register value to the counter and continues count- ing. Seiko Epson Corporation 14-3 S1C33L26 TECHNICAL MANUAL...
Page 178 TFMD[3:0] specifies the delay pattern to be inserted into a 16 underflow period. Inserting one delay extends the output clock cycle by one count clock cycle. This setting delays the interrupt timing in the same way. Seiko Epson Corporation 14-4 S1C33L26 TECHNICAL MANUAL...
Page 179 Notes: • The T8 module interrupt flag T8IF must be reset in the interrupt handler routine after a T8 in- terrupt has occurred to prevent recurring interrupts. • Reset T8IF before enabling T8 interrupts with T8IE to prevent occurrence of unwanted inter- rupt. T8IF is reset by writing 1. Seiko Epson Corporation 14-5 S1C33L26 TECHNICAL MANUAL...
Page 180: T8: T8 Interrupt Circuit
Set timer mode and start/stop timer 0x301168 T8_INT6 T8 Ch.6 Interrupt Control Register Control interrupt 0x301170 T8_CLK7 T8 Ch.7 Input Clock Select Register Select prescaler output clock 0x301172 T8_TR7 T8 Ch.7 Reload Data Register Set reload data Seiko Epson Corporation 14-6 S1C33L26 TECHNICAL MANUAL...
Page 181 (or between underflows). The time determined is used to obtain the desired wait time, the intervals between periodic interrupts or A/D triggers, and the pro- grammable serial interface transfer clock. Seiko Epson Corporation 14-7 S1C33L26 TECHNICAL MANUAL...
Page 182 D: Indicates the insertion of a delay cycle. Count clock Underflow signal (not corrected) Underflow signal (corrected) Delayed Output clock (not corrected) Output clock (corrected) Figure 14. 10.1 Delay Cycle Insertion in Fine Mode Seiko Epson Corporation 14-8 S1C33L26 TECHNICAL MANUAL...
Page 183 Enables or disables interrupts caused by counter underflows for each channel. 1 (R/W): Interrupt enabled 0 (R/W): Interrupt disabled (default) Setting T8IE to 1 enables T8 interrupt requests to the ITC; setting to 0 disables interrupts. D[7:1] Reserved Seiko Epson Corporation 14-9 S1C33L26 TECHNICAL MANUAL...
Page 184 No cause of interrupt has occurred (default) 1 (W): Flag is reset 0 (W): Ignored T8IF is the T8 interrupt flag that is set to 1 when the counter underflows. T8IF is reset by writing 1. Seiko Epson Corporation 14-10 S1C33L26 TECHNICAL MANUAL...
Page 185 16-bit PWM Timer (T16A5) 15.1 T16A5 Module Overview The S1C33L26 includes a 16-bit PWM timer (T16A5) module with two timer channels. The features of T16A5 are listed below. • 16-bit up counter with a comparator and capture unit • The count clock is selectable from 15 clocks output from the prescaler.
Page 186 Ch.0) dividing the PCLK1 clock into 1/1 to 1/16K and an external clock. Table 15. 3.1 Count Clock (PCLK1 Division Ratio) Selection CLKS[3:0] Division ratio CLKS[3:0] Division ratio External clock 1/128 1/16384 1/64 1/8192 1/32 1/4096 1/16 1/2048 1/1024 1/512 1/256 (Default: 0x0) Seiko Epson Corporation 15-2 S1C33L26 TECHNICAL MANUAL...
Page 187 A circuit uses the T16A_ATMA_x pin and the capture B circuit uses the T16A_ATMB_x pin. The T16A_ATMA_x and T16A_ATMB_x pins are shared with the timer outputs. They are configured for input when the system A or B is set to capture mode. Seiko Epson Corporation 15-3 S1C33L26 TECHNICAL MANUAL...
Page 188 Counter Control 15.5.1 Counter Reset The counter can be reset to 0 by writing 1 to PRESET/T16A_CTLx register. Normally, the counter should be reset by writing 1 to this bit before starting the count. Seiko Epson Corporation 15-4 S1C33L26 TECHNICAL MANUAL...
Page 189: T16A5: Reading Counter Values
Comparator mode PRUN PRESET T16A_ATMA_x T16A_ATMB_x Count clock T16A_TCx Reset Compare A Reset and Compare A Reset and interrupt compare B interrupt compare B interrupt interrupt Figure 15. 5.4.1 Operation Timing in Comparator Mode Seiko Epson Corporation 15-5 S1C33L26 TECHNICAL MANUAL...
Page 190 TOUT generation mode TOUTAMD[1:0]/T16A_CCCTLx register (for system A) or TOUTBMD[1:0]/T16A_CCCTLx register (for sys- tem B) is used to set how the TOUT signal is changed by the compare A and compare B signals. Seiko Epson Corporation 15-6 S1C33L26 TECHNICAL MANUAL...
Page 191 • Compare B interrupt (in comparator mode) • Capture A interrupt (in capture mode) • Capture B interrupt (in capture mode) • Capture A overwrite interrupt (in capture mode) • Capture B overwrite interrupt (in capture mode) Seiko Epson Corporation 15-7 S1C33L26 TECHNICAL MANUAL...
Page 192 CAPBOWIF will be set if the capture B register is overwritten when CAPBIF has been set regardless of whether the capture B register has been read or not. Therefore, be sure to reset CAPBIF immediately after the capture B register is read. Seiko Epson Corporation 15-8 S1C33L26 TECHNICAL MANUAL...
Page 193 The 16-bit PWM timer (T16A5) registers are described in detail below. These are 16-bit registers. Note: When data is written to the registers, the “Reserved” bits must always be written as 0 and not 1. Seiko Epson Corporation 15-9 S1C33L26 TECHNICAL MANUAL...
Page 194 1 Run 0 Stop D[15:14] Reserved D[13:12] DMASEL[1:0]: DMAC Channel Select Bits Selects the DMAC channels to be used for DMA transfer when a cause of compare A/B or capture A/B interrupt occurs. Seiko Epson Corporation 15-10 S1C33L26 TECHNICAL MANUAL...
Page 195 When CBUFEN is set to 1, compare data is written via the compare data buffer. The buffer contents are loaded into the compare A and compare B registers by the compare B signal. Seiko Epson Corporation 15-11 S1C33L26 TECHNICAL MANUAL...
Page 196 Note: The counter value must be read from the T16A_TCx register of the channel selected using T16SEL[1:0]/T16A_CTLx register. Seiko Epson Corporation 15-12 S1C33L26 TECHNICAL MANUAL...
Page 197 Writing 1 to TOUTBINV generates an active low signal (off level = high) for the TOUT B output. When TOUTBINV is 0, an active high signal (off level = low) is generated. TOUTBINV is a control bit for comparator mode and is ineffective in capture mode. Seiko Epson Corporation 15-13 S1C33L26 TECHNICAL MANUAL...
Page 198 When CCAMD is 0, the T16A_ CCAx register functions as the compare A register (comparator mode) for writing a comparison value to generate the compare A signal. Seiko Epson Corporation 15-14 S1C33L26 TECHNICAL MANUAL...
Page 199 CAPBTRG[1:0]/T16A_CCCTLx register, the captured value is loaded to this register. At the same time a capture B interrupt can be generated, thus the captured counter value can be read out in the interrupt handler. Seiko Epson Corporation 15-15 S1C33L26 TECHNICAL MANUAL...
Page 200 (16 bits) CAPAOWIF Capture A overwrite interrupt flag occurred occurred Interrupt Flag CAPBIF Capture B interrupt flag Register CAPAIF Capture A interrupt flag (T16A_IFLGx) CBIF Compare B interrupt flag CAIF Compare A interrupt flag Seiko Epson Corporation 15-16 S1C33L26 TECHNICAL MANUAL...
Page 201 Flag is reset 0 (W): Ignored CBIF is a T16A5 interrupt flag that is set to 1 when the counter reaches the value set in the compare B register. CBIF is reset by writing 1. Seiko Epson Corporation 15-17 S1C33L26 TECHNICAL MANUAL...
Page 202 Flag is reset 0 (W): Ignored CAIF is a T16A5 interrupt flag that is set to 1 when the counter reaches the value set in the compare A register. CAIF is reset by writing 1. Seiko Epson Corporation 15-18 S1C33L26 TECHNICAL MANUAL...
Page 203 16.1 T16P Module Overview The S1C33L26 incorporate a 16-bit audio PWM timer (T16P) that generates PWM pulses from PCM data. The pulses generated can be directly output to a low pass filter that eliminates quantization noise to shape the output signal into sound waveform.
Page 204 When using an external clock, the external clock cycle must be at least two CPU operating clock cycles. When an internal clock is used, it can be selected using CLKDIV[3:0]/T16P_CLK register from the 13 types gener- ated by the prescaler (PSC Ch.0) dividing the PCLK1 clock into 1/1 to 1/4,096. Seiko Epson Corporation 16-2 S1C33L26 TECHNICAL MANUAL...
Page 205 PWM_H pin and another generated from the low-order data bits is output from the PWM_L pin. When a split mode or 8-bit PCM data resolution is selected, compare A interrupts cannot be generated. Seiko Epson Corporation 16-3 S1C33L26 TECHNICAL MANUAL...
Page 206 When INITOL is 0 (default), the initial output level is low. When INITOL is set to 1, the initial output level is set to high. Note: Before the pin function is switched for T16P, be sure to set INITOL and then reset the T16P (set PRESET to 1). Seiko Epson Corporation 16-4 S1C33L26 TECHNICAL MANUAL...
Page 207 In fine mode (SELFM = 1) Output pulse width = CMPA × PCLK1 cycle × 1/2 (CMPA: CMPA[15:0] in normal mode, CMPA[15:n] or CMPA[(n-1):0] in split mode) 8-bit audio data should be written to CMPA[15:8] in 8-bit size. Seiko Epson Corporation 16-5 S1C33L26 TECHNICAL MANUAL...
Page 208 Note: It is possible to alter the VOLSEL[6:0] values during playing sound, note, however, that set VOL- SEL[6:0] before setting PRESET/T16P_CTL register if the first audio data must be output with volume controlled. Seiko Epson Corporation 16-6 S1C33L26 TECHNICAL MANUAL...
Page 209 PWM_L output (INITOL = 0) PWM_H output (INITOL = 1) PWM_L output (INITOL = 1) Buffer empty interrupt A match interrupt B match interrupt Figure 16. 4.6.2 PWM Output Timing Chart 2 (normal + fine mode) Seiko Epson Corporation 16-7 S1C33L26 TECHNICAL MANUAL...
Page 210 PWM_H output (INITOL = 1) PWM_L output (INITOL = 1) Buffer empty interrupt A match interrupt (not occurred) B match interrupt Figure 16. 4.6.4 PWM Output Timing Chart 4 (split + fine mode) Seiko Epson Corporation 16-8 S1C33L26 TECHNICAL MANUAL...
Page 211 Notes: • Reset the interrupt flag before enabling interrupts with the interrupt enable bit to prevent oc- currence of unwanted interrupt. The interrupt flag is reset by writing 1. • After an interrupt occurs, the interrupt flag in the T16P module must be reset in the interrupt handler routine. Seiko Epson Corporation 16-9 S1C33L26 TECHNICAL MANUAL...
Page 212 In fine mode (SELFM = 1) Output pulse width = CMPA × PCLK1 cycle × 1/2 (CMPA: CMPA[15:0] in normal mode, CMPA[15:n] or CMPA[(n-1):0] in split mode) 8-bit audio data should be written to CMPA[15:8] in 8-bit size. Seiko Epson Corporation 16-10 S1C33L26 TECHNICAL MANUAL...
Page 213 VOLSEL[6:0] before loading to the compare A register. If no volume control is required, set VOLBPS to 1. Note: When 8-bit PCM data is used, the volume control unit should be bypassed by setting VOLBPS to 1. Seiko Epson Corporation 16-11 S1C33L26 TECHNICAL MANUAL...
Page 214 Note: When signed audio data is selected, CMPA15/T16P_A register is treated as the sign bit for both 16-bit and 8-bit audio data. D[9:8] SPLTMD[1:0]: Split Mode Select Bits Selects the split mode for manipulating 16-bit PCM data. Seiko Epson Corporation 16-12 S1C33L26 TECHNICAL MANUAL...
Page 215 When INITOL is set to 1, the initial output level is set to high. Note: Before the pin function is switched for T16P, be sure to set INITOL and then reset the T16P (set PRESET to 1). Seiko Epson Corporation 16-13 S1C33L26 TECHNICAL MANUAL...
Page 216 To stop T16P being run, write 0 to PRUN. The compare data buffers/registers and counter retain the value at stop. The PWM output is fixed at the level set by INITOL. Note that T16P may not stop count- ing until B match conditions occur (BCNT[3:0] + 1) times. Seiko Epson Corporation 16-14 S1C33L26 TECHNICAL MANUAL...
Page 217 A register. BUFEF is reset by writing 1. Note, however, that the flag will be set to 1 again after resetting if the compare A buffer is still empty. Therefore, write compare data to the compare A buffer before resetting BUFEF. Seiko Epson Corporation 16-15 S1C33L26 TECHNICAL MANUAL...
Page 218 Enables or disables A match interrupts. 1 (R/W): Interrupt enabled 0 (R/W): Interrupt disabled (default) Setting INTAEN to 1 enables A match interrupt requests to the ITC. Setting it to 0 disables interrupts. Seiko Epson Corporation 16-16 S1C33L26 TECHNICAL MANUAL...
Page 219 Watchdog Timer (WDT) 17.1 WDT Module Overview The S1C33L26 incorporates a watchdog timer to detect the CPU running uncontrollably. The features of WDT are listed below. • 30-bit up counter with a comparator • Reset or NMI can be generated when the counter reaches the specified value if WDT has not been reset.
Page 220 To rewrite these registers, write protection must be removed by writing 0x96 to WDPTC[15:0]/WD_PROTECT register in 16-bit access only. Once the registers are rewritten, be sure to write other than 0x96 to WDPTC[15:0] to reapply write protection. Seiko Epson Corporation 17-2 S1C33L26 TECHNICAL MANUAL...
Page 221 When the watchdog timer is reset in software, clock output from the IC goes low at that time and remains low. Input clock Counter data FFFF1D FFFF1E FFFF1F FFFF20 FFFF1F FFFF20 Comparison data FFFF20 Comparison match signal WDT_CLK output clock Figure 17. 4.5.1 Clock Output of Watchdog Timer Seiko Epson Corporation 17-3 S1C33L26 TECHNICAL MANUAL...
Page 222 WDPTC[15:0] is set to other than 0x96. When the WDT_EN, WDT_CMP_L, or WDT_CMP_H have been rewritten, be sure to write other than 0x96 to WDPTC[15:0] to prevent erro- neous writing to the registers. Seiko Epson Corporation 17-4 S1C33L26 TECHNICAL MANUAL...
Page 223 Setting this bit to 1 outputs a reset signal (a pulse 32 system clocks in width) to the CMU when the count of the up-counter matches the value set in the comparison data register. Setting this bit to 0 out- puts no reset signals. Seiko Epson Corporation 17-5 S1C33L26 TECHNICAL MANUAL...
Page 224 With NMI or reset signal output enabled, the watchdog timer must be reset by writing 1 to this bit with- in the set NMI/reset generation cycle. The up-counter is thereby reset to 0, then starts counting NMI/ reset generation cycles all over again. Seiko Epson Corporation 17-6 S1C33L26 TECHNICAL MANUAL...
Page 225 Universal Serial Interface (USI) 18.1 USI Module Overview The S1C33L26 incorporates a universal serial interface (USI) module that can be configured as a UART, SPI, or C interface unit by the software switch. The following shows the main features of USI: •...
Page 226 (or sampling clock). Be aware that the division ratio in the USI depends on the interface mode. When the USI is configured to an SPI master (fast mode) device, PCLK1 is used as the source clock. Seiko Epson Corporation 18-2 S1C33L26 TECHNICAL MANUAL...
Page 227 C slave occupies the SCL line for two source clock (T8 output clock) cycles by driving it to low after detecting that the I C mas- ter drives the SCL line to low. Seiko Epson Corporation 18-3 S1C33L26 TECHNICAL MANUAL...
Page 228 Use LSBFST/USI_GCFG register to select whether the data MSB or LSB is input/output first. LSB first is selected when LSBFST is set to 0 (default). MSB first is selected when LSBFST is set to 1. Seiko Epson Corporation 18-4 S1C33L26 TECHNICAL MANUAL...
Page 229: Usi: Settings For Spi Mode
Setting it to 0 (default) treats it as active high. The SPI clock phase can be selected using SCPHA/USI_SCFG register. These control bits set transfer timing as shown in Figure 18.4.5.1. Seiko Epson Corporation 18-5 S1C33L26 TECHNICAL MANUAL...
Page 230 The data length in SPI slave mode is fixed at 8 bits. 18.4.6 Settings for I C Mode The I C mode does not need to set data format and other conditions. The data length in I C mode is fixed at 8 bits. Seiko Epson Corporation 18-6 S1C33L26 TECHNICAL MANUAL...
Page 231 The URBSY flag indicates the shift register status. This flag is set to 1 while data is being received in the shift register and reverts to 0 once the received data is loaded to the receive data buffer. Read this flag to check whether the receiver circuit is operating or at standby. Seiko Epson Corporation 18-7 S1C33L26 TECHNICAL MANUAL...
Page 232: Usi: Data Receiving Timing Chart (Uart Mode)
USI_DO pin SSIF (master mode) STDIF Reset by writing 1 Reset by writing 1 Interrupt (MSB first) Transmit buffer empty interrupt Transmit buffer empty interrupt Figure 18. 5.2.1 Data Transmission Timing Chart (SPI mode) Seiko Epson Corporation 18-8 S1C33L26 TECHNICAL MANUAL...
Page 233: Usi: Data Receiving Timing Chart (Spi Mode)
1 when the slave select signal is inactive (high); it goes 0 when the slave select signal is active (low). If a slave select output is required in SPI master mode, use a general-purpose I/O port and control its output with software. Seiko Epson Corporation 18-9 S1C33L26 TECHNICAL MANUAL...
Page 234 START Generate start condition Send slave address and transfer direction bit ACK received? Send data ACK received? Error handling Finished? Generate stop condition Figure 18. 5.3.1 I C Master Data Transmission Flow Chart Seiko Epson Corporation 18-10 S1C33L26 TECHNICAL MANUAL...
Page 235: Usi: Sending Slave Address And Transfer Direction Bit (Old)
7-bit address mode. In 10-bit mode, data is sent twice or three times under software control. Figure 18.5.3.4 shows the configura- tion of the address data. Seiko Epson Corporation 18-11 S1C33L26 TECHNICAL MANUAL...
Page 236 This trigger transfers the buffer data to the transmit shift register to start transmission. The module starts clock output from the USI_CK pin. The data in the shift register is shifted in sequence with the clock and sent from the USI_DO pin. Seiko Epson Corporation 18-12 S1C33L26 TECHNICAL MANUAL...
Page 237 START Generate start condition Send slave address and transfer direction bit ACK received? Receive data Error handling Send ACK Finished? Generate stop condition Figure 18. 5.3.8 I C Master Data Receiving Flow Chart Seiko Epson Corporation 18-13 S1C33L26 TECHNICAL MANUAL...
Page 238 Repeat an 8-bit data reception and ACK (NAK) transmission for the required number of times. (4) Generating stop condition The procedure is the same as that of data transmission in I C master mode. Seiko Epson Corporation 18-14 S1C33L26 TECHNICAL MANUAL...
Page 239: Usi: Control Method In I 2 C Slave Mode
NAK has been received. ACK has been received. ACK or NAK has been sent. End of receive data. End of transmit data. Stop condition has been detected. Start condition has been detected. (Default: 0x0) Seiko Epson Corporation 18-15 S1C33L26 TECHNICAL MANUAL...
Page 240 Note: The timing chart above shows a basic transfer operation that does not include an actual I C trans- fer procedure. See “Receiving control byte in I C slave mode” in “18.9 Precautions.” Seiko Epson Corporation 18-16 S1C33L26 TECHNICAL MANUAL...
Page 241 (4) When a stop condition is received If the ISSTA[2:0] value read during data transmission is 0x1, the I C master device has generated a stop condition (see Figure 18.5.3.6). In this case, abort data transmission. Seiko Epson Corporation 18-17 S1C33L26 TECHNICAL MANUAL...
Page 242 Note: The timing chart above shows a basic transfer operation that does not include an actual I C trans- fer procedure. See “Receiving control byte in I C slave mode” in “18.9 Precautions.” Seiko Epson Corporation 18-18 S1C33L26 TECHNICAL MANUAL...
Page 243 (an overrun error occurs at the time the first bit of the third byte is fetched). Seiko Epson Corporation 18-19 S1C33L26 TECHNICAL MANUAL...
Page 244 USI (UART mode) interrupt is attributable to a transmit buffer empty. If UTDIF is 1, the next trans- mit data can be written to the transmit data buffer by the interrupt handler routine. Seiko Epson Corporation 18-20 S1C33L26 TECHNICAL MANUAL...
Page 245 Receive error interrupt To use this interrupt, set SEIE/USI_SIE register to 1. If SEIE is set to 0 (default), interrupt requests for this cause will not be sent to the ITC. Seiko Epson Corporation 18-21 S1C33L26 TECHNICAL MANUAL...
Page 246 • Receive error interrupt Operation completion interrupt To use this interrupt, set ISIE/USI_ISIE register to 1. If ISIE is set to 0 (default), interrupt requests for this cause will not be sent to the ITC. Seiko Epson Corporation 18-22 S1C33L26 TECHNICAL MANUAL...
Page 247 C Master Mode Trigger Register Starts I C master operations. 0x300461 USI_IMIE USI I C Master Mode Interrupt Enable Register Enables interrupts. 0x300462 USI_IMIF USI I C Master Mode Interrupt Flag Register Indicates interrupt occurrence status. Seiko Epson Corporation 18-23 S1C33L26 TECHNICAL MANUAL...
Page 248 The data written to this register is converted into serial data through the shift register and is output from the USI_DO pin with the bit set to 1 as high level and the bit set to 0 as low level. Seiko Epson Corporation 18-24 S1C33L26 TECHNICAL MANUAL...
Page 249 Setting UPREN to 1 parity-checks the received data. A parity bit is automati- cally added to the transmit data. If UPREN is set to 0, no parity bit is checked or added. Seiko Epson Corporation 18-25 S1C33L26 TECHNICAL MANUAL...
Page 250 Inspect URBSY to determine whether the receiving circuit is operating or at standby. UTBSY: Transmit Busy Flag Bit Indicates the USI status in UART mode. 1 (R): Busy 0 (R): Idle (default) Seiko Epson Corporation 18-26 S1C33L26 TECHNICAL MANUAL...
Page 251 (when transmission starts), indicating that the next transmit data can be written to. At the same time a transmit buffer empty interrupt request is sent to the ITC if UTDIE/USI_UIE register is 1. UTDIF is reset by writing 1. Seiko Epson Corporation 18-27 S1C33L26 TECHNICAL MANUAL...
Page 252 USI_CK (SCPOL = 1, SCPHA = 1) USI_CK (SCPOL = 1, SCPHA = 0) USI_CK (SCPOL = 0, SCPHA = 1) USI_CK (SCPOL = 0, SCPHA = 0) USI_DI/USI_DO D7 (MSB) D0 (LSB) Fetching received data into shift register Seiko Epson Corporation 18-28 S1C33L26 TECHNICAL MANUAL...
Page 253 Enables interrupt requests to the ITC when data written to the transmit data buffer is sent to the shift register (i.e. when data transmission begins). 1 (R/W): Enabled 0 (R/W): Disabled (default) Set this bit to 1 to write data to the transmit data buffer using interrupts. Seiko Epson Corporation 18-29 S1C33L26 TECHNICAL MANUAL...
Page 254 At the same time a receive buffer full interrupt request is sent to the ITC if SRDIE/USI_SIE register is 1. SRDIF is reset by writing 1. Seiko Epson Corporation 18-30 S1C33L26 TECHNICAL MANUAL...
Page 255 Selects an I C master operation. Table 18. 8.3 Trigger List in I C Master Mode IMTGMOD[2:0] Trigger Reserved ACK/NAK reception NAK transmission ACK transmission Data reception Data transmission Stop condition Start condition (Default: 0x0) Seiko Epson Corporation 18-31 S1C33L26 TECHNICAL MANUAL...
Page 256 C master operation) sets IMBSY to 1 indicating that the I C controller is busy (operating). When the specified operation has finished, IMBSY is reset to 0. D[4:2] IMSTA[2:0]: I C Master Status Bits Indicates the I C master status. Seiko Epson Corporation 18-32 S1C33L26 TECHNICAL MANUAL...
Page 257 Transmit data reserved Wait for start Note: This register is effective only in I C slave mode. Configure USI to I C slave mode before this reg- ister can be used. D[7:5] Reserved Seiko Epson Corporation 18-33 S1C33L26 TECHNICAL MANUAL...
Page 258 Enables interrupt requests to the ITC when the triggered operation has completed. 1 (R/W): Enabled 0 (R/W): Disabled (default) Set this bit to 1 to confirm whether the triggered operation has completed or not using interrupts. Seiko Epson Corporation 18-34 S1C33L26 TECHNICAL MANUAL...
Page 259 ISEIF is reset by writing 1. To reset an overrun error, clear ISEIF by writing 1, and then read the receive data buffer (USI_RD regis- ter) twice. Seiko Epson Corporation 18-35 S1C33L26 TECHNICAL MANUAL...
Page 260 0, set ISTGMOD[2:0]/USIL_ISTG register to 0x0 and ISTG/USIL_ISTG register to 1 to wait for a start condition that will be sent from the master for reading data (for the slave to sent the read data). Seiko Epson Corporation 18-36 S1C33L26 TECHNICAL MANUAL...
Page 261 Interface (USIL) 19.1 USIL Module Overview The S1C33L26 incorporates a USIL module that can be configured as a UART, SPI, I C, LCD SPI, and LCD paral- lel interface unit by the software switch. The following shows the main features of USIL: •...
Page 262 Inputs/outputs serial data from/to the I C bus. (*) C slave i2c_sda LCD SPI – – Not used LCD parallel lcdp_cs Chip select signal output pin Outputs the chip select signal to the LCD driver/panel. Seiko Epson Corporation 19-2 S1C33L26 TECHNICAL MANUAL...
Page 263 UART mode, I C master mode × DF / {(TR + 1) × 8 + TFMD} bps = f SYS_CLK × DF / bps - TFMD - 8) / 8 TR = (f SYS_CLK Seiko Epson Corporation 19-3 S1C33L26 TECHNICAL MANUAL...
Page 264 The figure below shows an example in which the timing becomes worse. T8 output clock SCL controlled by I C master SCL controlled by I C slave USIL_CK pin Figure 19. 3.2 Example of Delayed I C Clock Seiko Epson Corporation 19-4 S1C33L26 TECHNICAL MANUAL...
Page 265 Stop bit Use USTPB/USIL_UCFG register to select the stop bit length. Setting USTPB to 0 (default) configures the stop bit length to 1 bit. Setting USTPB to 1 configures it to 2 bits. Seiko Epson Corporation 19-5 S1C33L26 TECHNICAL MANUAL...
Page 266 USIL_CK (SCPOL = 1, SCPHA = 1) USIL_CK (SCPOL = 1, SCPHA = 0) USIL_CK (SCPOL = 0, SCPHA = 1) USIL_CK (SCPOL = 0, SCPHA = 0) USIL_DI/USIL_DO D7 (MSB) D0 (LSB) Fetching received data into shift register Seiko Epson Corporation 19-6 S1C33L26 TECHNICAL MANUAL...
Page 267 In LCD SPI mode, the display data format can be selected using LSDMOD[1:0]/USIL_LSDCFG register. Table 19. 4.7.1 LCD SPI Data Mode LSDMOD[1:0] Data mode 24-bit mode 18-bit mode 16-bit mode 8-bit mode (Default: 0x0) Seiko Epson Corporation 19-7 S1C33L26 TECHNICAL MANUAL...
Page 268 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 (BGR mode) B5 B4 B3 B2 B1 G5 G4 G3 G2 G1 G0 R5 R4 R3 R2 R1 18-bit Format 1 Seiko Epson Corporation 19-8 S1C33L26 TECHNICAL MANUAL...
Page 269 LCD_D[7:0] (RD) USIL_DO (lcdp_wr) valid LCD_D[7:0] (WR) Setup cycle Wait cycle Hold cycle Figure 19. 4.8.1 Access Timing Parameters Setup cycle The setup cycle can be set to 1–4 cycles using LPST[1:0]/USIL_LPAC register. Seiko Epson Corporation 19-9 S1C33L26 TECHNICAL MANUAL...
Page 270 The UTBSY flag indicates the USIL status in UART mode. This flag switches to 1 when transmit data is writ- ten to the transmit buffer and reverts to 0 after both the shift register and transmit buffer become empty. Seiko Epson Corporation 19-10 S1C33L26 TECHNICAL MANUAL...
Page 271 (see Figure 19.4.5.1) and sent from the USIL_ DO pin. The SPI controller includes two status flags for transfer control: STDIF/USIL_SIF register and SSIF/USIL_SIF register. Seiko Epson Corporation 19-11 S1C33L26 TECHNICAL MANUAL...
Page 272 In SPI master mode, the SSIF flag indicates the shift register status. This flag switches to 1 at the beginning of data reception and reverts to 0 once the data is received. Read this flag to check whether the SPI controller is operating or at standby. Seiko Epson Corporation 19-12 S1C33L26 TECHNICAL MANUAL...
Page 273 IMIF register) is also set to 1. After an interrupt occurs, read the status bits (IMSTA[2:0]/USIL_IMIF register) to check the operation finished. Then clear IMIF by writing 1. IMSTA[2:0] will be automatically cleared to 0x0. Seiko Epson Corporation 19-13 S1C33L26 TECHNICAL MANUAL...
Page 274 USIL_DI pin (input) IMTGMOD[2:0] IMTG (write) IMBSY IMSTA[2:0] TD[7:0] Address Transfer data 1 IMIF Start interrupt End of transmission Receive End of transmission interrupt ACK interrupt interrupt (1) Start condition → Data transmission Seiko Epson Corporation 19-14 S1C33L26 TECHNICAL MANUAL...
Page 275 C master performs data reception, issue a repeated start condition after the second data has been sent and then send the third data as shown below. Third transmit data 2 high order slave address bits Figure 19. 5.3.4 Transmit Data Specifying Slave Address and Transfer Direction Seiko Epson Corporation 19-15 S1C33L26 TECHNICAL MANUAL...
Page 276 SCL line is maintained at high and the SDA line is pulled up from low to high. To generate a stop condition in this I C master, set IMTGMOD[2:0] to 0x1 and write 1 to IMTG. SDA (USIL_DI) SCL (USIL_CK) Stop condition Figure 19. 5.3.6 Stop Condition Seiko Epson Corporation 19-16 S1C33L26 TECHNICAL MANUAL...
Page 277 A0 R/W = 1 USIL_DI pin (input) IMTGMOD[2:0] IMTG (write) IMBSY IMSTA[2:0] TD[7:0] Address RD[7:0] IMIF Start interrupt End of transmission Receive End of reception interrupt ACK interrupt interrupt (1) Start condition → Data reception Seiko Epson Corporation 19-17 S1C33L26 TECHNICAL MANUAL...
Page 278 The procedure is the same as that of data transmission in I C master mode. (5) Generating repeated start condition The procedure is the same as that of data transmission in I C master mode. Seiko Epson Corporation 19-18 S1C33L26 TECHNICAL MANUAL...
Page 279 NAK has been received. ACK has been received. ACK or NAK has been sent. End of receive data. End of transmit data. Stop condition has been detected. Start condition has been detected. (Default: 0x0) Seiko Epson Corporation 19-19 S1C33L26 TECHNICAL MANUAL...
Page 280 Note: The timing chart above shows a basic transfer operation that does not include an actual I C trans- fer procedure. See “Receiving control byte in I C slave mode” in “19.9 Precautions.” Seiko Epson Corporation 19-20 S1C33L26 TECHNICAL MANUAL...
Page 281 (4) When a stop condition is received If the ISSTA[2:0] value read during data transmission is 0x1, the I C master device has generated a stop condition (see Figure 19.5.3.6). In this case, abort data transmission. Seiko Epson Corporation 19-21 S1C33L26 TECHNICAL MANUAL...
Page 282 Note: The timing chart above shows a basic transfer operation that does not include an actual I C trans- fer procedure. See “Receiving control byte in I C slave mode” in “19.9 Precautions.” Seiko Epson Corporation 19-22 S1C33L26 TECHNICAL MANUAL...
Page 283 The LSBSY flag indicates the USIL status in LCD SPI mode. This flag switches to 1 when transmit data is written to the transmit buffer and reverts to 0 after data transfer for the data size set using LSDMOD[1:0]/USIL_LSDCFG register has completed. Seiko Epson Corporation 19-23 S1C33L26 TECHNICAL MANUAL...
Page 284 Figure 19. 5.5.1 Data-Write Timing Chart (LCD parallel mode) Data read To read data from the LCD driver/panel via the LCD parallel interface, issue a read trigger by writing 1 to LPRD/USIL_LPCFG register. Seiko Epson Corporation 19-24 S1C33L26 TECHNICAL MANUAL...
Page 285 Note: After successive data reading has been terminated, there are 2 or 3 data remained in the read buffer. Be sure to read them as shown in the flow chart (Figure 19.5.5.4). Seiko Epson Corporation 19-25 S1C33L26 TECHNICAL MANUAL...
Page 286 Read data from USIL RD register (LPRD ← 1) LPRDIF = 1? Clear read buffer full flag (LPRDIF ← 1) Read data from USIL RD register Read completed? Figure 19. 5.5.4 Successive Read Flow Chart (LCD parallel mode) Seiko Epson Corporation 19-26 S1C33L26 TECHNICAL MANUAL...
Page 287 However, the received data cannot be guaranteed if a parity error occurs. The UPEIF flag is reset to 0 by writing 1. Seiko Epson Corporation 19-27 S1C33L26 TECHNICAL MANUAL...
Page 288 Interrupts in SPI Mode The SPI master/slave modes include a function for generating the following three different types of interrupts. • Transmit buffer empty interrupt • Receive buffer full interrupt • Receive error interrupt Seiko Epson Corporation 19-28 S1C33L26 TECHNICAL MANUAL...
Page 289 NAK has been received. ACK has been received. ACK or NAK has been sent. End of receive data. End of transmit data. Stop condition has been generated. Start condition has been generated. (Default: 0x0) Seiko Epson Corporation 19-29 S1C33L26 TECHNICAL MANUAL...
Page 290 C slave mode) interrupt was caused by a receive error. If ISEIF is 1, the inter- rupt handler routine will proceed with error recovery. To reset an overrun error, clear ISEIF by writing 1, and then read the receive data buffer (USIL_RD register) twice. Seiko Epson Corporation 19-30 S1C33L26 TECHNICAL MANUAL...
Page 291 USIL transmit (write) buffer empty: DMAC Ch.7 For more information on DMA transfer, see the “DMA Controller (DMAC)” chapter. Note: The USIL module cannot invoke a DMA in I C master and slave mode. Seiko Epson Corporation 19-31 S1C33L26 TECHNICAL MANUAL...
Page 292 Selects whether serial data will be transferred from the MSB or LSB. 1 (R/W): MSB first 0 (R/W): LSB first (default) This setting affects all interface modes. D[2:0] USILMOD[2:0]: Interface Mode Configuration Bits Selects an interface mode. Seiko Epson Corporation 19-32 S1C33L26 TECHNICAL MANUAL...
Page 293 0 7 bits Configuration USTPB Stop bit select 1 2 bits 0 1 bit Register UPMD Parity mode select 1 Even 0 Odd (USIL_UCFG) UPREN Parity enable 1 With parity 0 No parity Seiko Epson Corporation 19-33 S1C33L26 TECHNICAL MANUAL...
Page 294 Enables interrupt requests to the ITC when received data is loaded to the receive data buffer. 1 (R/W): Enabled 0 (R/W): Disabled (default) Set this bit to 1 to read received data using interrupts. Seiko Epson Corporation 19-34 S1C33L26 TECHNICAL MANUAL...
Page 295 USEIF is set to 1 when a framing error occurs. At the same time a receive error interrupt request is sent to the ITC if UEIE/USIL_UIE register is 1. A framing error occurs when data is received with the stop bit set to 0. USEIF is reset by writing 1. Seiko Epson Corporation 19-35 S1C33L26 TECHNICAL MANUAL...
Page 296 Set the data transfer timing together with SCPOL. (See Figure 19.8.1.) SCPOL: Clock Polarity Select Bit Selects the SPI clock polarity. 1 (R/W): Active low 0 (R/W): Active high (default) Set the data transfer timing together with SCPHA. (See Figure 19.8.1.) Seiko Epson Corporation 19-36 S1C33L26 TECHNICAL MANUAL...
Page 297 SEIE: Receive Error Interrupt Enable Bit Enables interrupt requests to the ITC when an overrun error occurs. 1 (R/W): Enabled 0 (R/W): Disabled (default) Set this bit to 1 to process overrun errors using interrupts. Seiko Epson Corporation 19-37 S1C33L26 TECHNICAL MANUAL...
Page 298 An overrun error occurs if the third byte data is received in this condi- tion, as the second byte data in the shift register is corrupted (an overrun error occurs at the time the first bit of the third byte is fetched). Seiko Epson Corporation 19-38 S1C33L26 TECHNICAL MANUAL...
Page 299 C master operation using IMTGMOD[2:0] and write 1 to IMTG as the trigger. The I C con- troller controls the I C bus to generate the specified operating status. Reserved D[2:0] IMTGMOD[2:0]: I C Master Trigger Mode Select Bits Selects an I C master operation. Seiko Epson Corporation 19-39 S1C33L26 TECHNICAL MANUAL...
Page 300 C master mode. Configure USIL to I C master mode before this register can be used. D[7:6] Reserved IMBSY: I C Master Busy Flag Bit Indicates the I C master operation status. 1 (R): Busy 0 (R): Standby (default) Seiko Epson Corporation 19-40 S1C33L26 TECHNICAL MANUAL...
Page 301 0 when being read. D2–0 ISTGMOD C slave trigger mode select ISTGMOD[2:0] Trigger mode 0x0 R/W [2:0] reserved Receive ACK/NAK Transmit NAK Transmit ACK Receive data/ Detect stop Transmit data reserved Wait for start Seiko Epson Corporation 19-41 S1C33L26 TECHNICAL MANUAL...
Page 302 Enables interrupt requests to the ITC when the triggered operation has completed. 1 (R/W): Enabled 0 (R/W): Disabled (default) Set this bit to 1 to confirm whether the triggered operation has completed or not using interrupts. Seiko Epson Corporation 19-42 S1C33L26 TECHNICAL MANUAL...
Page 303 ISEIF is reset by writing 1. To reset an overrun error, clear ISEIF by writing 1, and then read the receive data buffer (USIL_RD reg- ister) twice. Seiko Epson Corporation 19-43 S1C33L26 TECHNICAL MANUAL...
Page 304 When LSCMDEN is set to 1, data is prefixed with a command bit (1 bit). The command bit is used for controlling the SPI LCD driver/panel connected to the USIL. The command bit value to be transmitted can be specified using LSCMD. Seiko Epson Corporation 19-44 S1C33L26 TECHNICAL MANUAL...
Page 305 (when transmission starts), indicating that the next transmit data can be written to. At the same time a transmit buffer empty interrupt request is sent to the ITC if LSTDIE/USIL_LSIE register is 1. LSTDIF is reset by writing 1. Seiko Epson Corporation 19-45 S1C33L26 TECHNICAL MANUAL...
Page 306 R5 R4 R3 R2 R1 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 (BGR mode) B5 B4 B3 B2 B1 G5 G4 G3 G2 G1 G0 R5 R4 R3 R2 R1 Figure 19. 8.5 16-bit Data Format Seiko Epson Corporation 19-46 S1C33L26 TECHNICAL MANUAL...
Page 307 LPSRDEN Successive read enable 1 Enable 0 Disable Mode Configu- LPCMD Command bit 1 High 0 Low ration Register LPRD Read trigger 1 Trigger 0 Ignored (USIL_LPCFG) 1 Read cycle 0 Read finished Seiko Epson Corporation 19-47 S1C33L26 TECHNICAL MANUAL...
Page 308 Enables interrupt requests to the ITC when data written to the write (transmit data) buffer is output via the LCD_D[7:0] pins. 1 (R/W): Enabled 0 (R/W): Disabled (default) Set this bit to 1 to write data to the write buffer using interrupts. Seiko Epson Corporation 19-48 S1C33L26 TECHNICAL MANUAL...
Page 309 LPWT[3:0] Wait cycle 0x0 R/W 15 cycles 14 cycles 1 cycle 0 cycles Note: This register is effective only in LCD parallel mode. Configure USIL to LCD parallel mode before setting this register. Seiko Epson Corporation 19-49 S1C33L26 TECHNICAL MANUAL...
Page 310 (Default: 0x0) T8 Ch.3 output clock USIL_CS (lcdp_cs) valid USIL_DI (lcdp_a0) USIL_CK (lcdp_rd) valid LCD_D[7:0] (RD) USIL_DO (lcdp_wr) valid LCD_D[7:0] (WR) Setup cycle Wait cycle Hold cycle Figure 19. 4.8.8 Access Timing Parameters Seiko Epson Corporation 19-50 S1C33L26 TECHNICAL MANUAL...
Page 311 0, set ISTGMOD[2:0]/USIL_ISTG register to 0x0 and ISTG/USIL_ISTG register to 1 to wait for a start condition that will be sent from the master for reading data (for the slave to sent the read data). Seiko Epson Corporation 19-51 S1C33L26 TECHNICAL MANUAL...
Page 312 General-Purpose Serial Interface (FSIO) 20.1 FSIO Module Overview The S1C33L26 contains two channels (Ch.0 and Ch.1) of serial interfaces, the features of which are described be- low. • A clock-synchronized or asynchronous mode can be selected for the transfer method.
Page 313 When using the IrDA interface, set the transfer mode for the asynchronous 7-bit or asynchronous 8-bit mode. The input/output pins are configured differently, depending on the transfer mode. The pin configuration in each mode is shown in Table 20.4.1.2. Seiko Epson Corporation 20-2 S1C33L26 TECHNICAL MANUAL...
Page 314 Standard Mode and Advanced Mode The serial interface in the S1C33L26 is extended from that of the C33 STD models. This serial interface has two operating modes, standard (STD) mode of which functions are compatible with the existing C33 STD models and an advanced (ADV) mode allowing use of the extended functions.
Page 315 Master and slave modes Either the clock-synchronized master mode or the clock-synchronized slave mode can be selected using SMD[1:0]/FSIO_CTLx register. Seiko Epson Corporation 20-4 S1C33L26 TECHNICAL MANUAL...
Page 316 “FSIO Interrupts and DMA.” Note: Always make sure the serial interface is inactive (TXEN/FSIO_CTLx register and RXEN/FSIO_ CTLx register = 0) before these settings are made. A change of settings during operation may cause a malfunction. Seiko Epson Corporation 20-5 S1C33L26 TECHNICAL MANUAL...
Page 317 FSIO_CTLx register) cannot be enabled simultaneously. When transmitting data, fix RXEN at 0 and do not change it during a transmit operation. In addition, make sure that TXEN is not set to 0 during a transmit operation. Seiko Epson Corporation 20-6 S1C33L26 TECHNICAL MANUAL...
Page 318 2. If #SRDYx is on a low level, the synchronizing clock input to the serial interface begins. The synchro- nizing clock is also output from the SCLKx pin to the slave device. Seiko Epson Corporation 20-7 S1C33L26 TECHNICAL MANUAL...
Page 319 The synchronizing clock input/output on the SCLKx pin also is enabled (ready for input/output). Receive operations are disabled and the receive data buffer (FIFO) is cleared by writing 0 to RXEN. Seiko Epson Corporation 20-8 S1C33L26 TECHNICAL MANUAL...
Page 320 2, 3, 4, 5 Data read RXDNUM[1:0] RDBF #SRDYx (SRDYCTL = 0) Receive-buffer full interrupt request Overrun error (FIFOINT[1:0] = 2) interrupt request DMA trigger timings Figure 20. 6.3.3 Receive Timing Chart in Clock-Synchronized Master Mode Seiko Epson Corporation 20-9 S1C33L26 TECHNICAL MANUAL...
Page 321 Generation of overrun error can be disabled by controlling the #SRDYx as shown below. Seiko Epson Corporation 20-10 S1C33L26 TECHNICAL MANUAL...
Page 322 This operation clears (initializes) the receive data buffer (FIFO), therefore, make sure that there is no data that has not been read in the receive data buffer before setting RXEN to 0. Seiko Epson Corporation 20-11 S1C33L26 TECHNICAL MANUAL...
Page 323 (Stop bit: 2 bits, parity: used) s1: start bit, s2 & s3: stop bit, p: parity bit Figure 20. 7.1.2 Data Format for Asynchronous Transfer Serial data is transmitted and received, starting with the LSB. Seiko Epson Corporation 20-12 S1C33L26 TECHNICAL MANUAL...
Page 324 Sampling clock In the asynchronous mode, SIO_CLK (the clock output by the baud-rate timer or input from the SCLKx pin) is internally divided in the serial interface, in order to create a sampling clock. Seiko Epson Corporation 20-13 S1C33L26 TECHNICAL MANUAL...
Page 325 2 bits 2 bits Even 2 bits None 1 bit 1 bit Even 1 bit None * PMD settings are ineffective when EPR = 0. (Default: STPB = EPR = PMD = 0) Seiko Epson Corporation 20-14 S1C33L26 TECHNICAL MANUAL...
Page 326 DMA, the data prepared in memory can be transmitted successively to the transmit-data register through DMA transfers. For details on how to control interrupts and DMA requests, refer to Section 20.9, “FSIO Interrupts and DMA.” Figure 20.7.3.1 shows a transmit timing chart in the asynchronous mode. Seiko Epson Corporation 20-15 S1C33L26 TECHNICAL MANUAL...
Page 327 Since an interrupt can be generated by setting the interrupt control bits, the received data can be read by an interrupt processing routine. Seiko Epson Corporation 20-16 S1C33L26 TECHNICAL MANUAL...
Page 328 If data with a stop bit = 0 is received, the serial interface assumes that the data is out of synchronization and generates a framing error. If two stop bits are used, only the first stop bit is checked. When this error occurs, the framing-error flag FER/FSIO_STATUSx register is set to 1. Seiko Epson Corporation 20-17 S1C33L26 TECHNICAL MANUAL...
Page 329 Since the contents of the asynchronous mode are applied directly for the serial-interface functions other than the IrDA interface unit, refer to Section 20.7, “Asynchronous Interface,” for details on how to set and control the data formats and data transfers. Seiko Epson Corporation 20-18 S1C33L26 TECHNICAL MANUAL...
Page 330 IRRL/FSIO_IRDAx register and IRTL/FSIO_IRDAx register, respectively. The logic of the input/output signal is inverted by writing 1 to IRRL/IRTL. Logic is not inverted if the bit is set to 0. Seiko Epson Corporation 20-19 S1C33L26 TECHNICAL MANUAL...
Page 331 During data reception, the pulse width of the input signal from SINx is set to 16/3 before the signal is trans- ferred to the serial interface. SIO_CLK 1 2 3 4 RZI modulator input (SINx) 3 × SIO_CLK RZI modulator output (I/F input) 16 × SIO_CLK Figure 20. 8.3.2 Demodulation by RZI Circuit Seiko Epson Corporation 20-20 S1C33L26 TECHNICAL MANUAL...
Page 332 Receive error interrupt To use this interrupt, set RERR_IE/FSIO_INTEx register to 1. If RERR_IE is set to 0 (default), interrupt re- quests for this cause will not be sent to the ITC. Seiko Epson Corporation 20-21 S1C33L26 TECHNICAL MANUAL...
Page 333 Select standard/advanced mode The FSIO registers are described in detail below. These are 8-bit registers. Note: When data is written to the registers, the “Reserved” bits must always be written as 0 and not 1. Seiko Epson Corporation 20-22 S1C33L26 TECHNICAL MANUAL...
Page 334 Receive data buffer status flag 1 Contained 0 Not contained D[7:6] RXDNUM[1:0]: Receive FIFO Data Count Bits Indicates the number of data in the receive data buffer (FIFO) that have not been read. Seiko Epson Corporation 20-23 S1C33L26 TECHNICAL MANUAL...
Page 335 OER: Overrun Error Flag Bit Indicates whether an overrun error has occurred. 1 (R): An error occurred 0 (R): No error occurred (default) 1 (W): Has no effect 0 (W): Reset to 0 Seiko Epson Corporation 20-24 S1C33L26 TECHNICAL MANUAL...
Page 336 Writing 0 to RXEN clears the receive data buffer (FIFO) as well as disabling receive operations. EPR: Parity Enable Bit Selects a parity function for asynchronous transfer. 1 (R/W): Parity added 0 (R/W): No parity added (default) Seiko Epson Corporation 20-25 S1C33L26 TECHNICAL MANUAL...
Page 337 0 Direct R/W Valid only in async IRRL mode. IrDA I/F input logic inversion 1 Inverted 0 Direct D1–0 IRMD[1:0] Interface mode select IRMD[1:0] I/F mode 0x0 R/W reserved IrDA 1.0 reserved General I/F Seiko Epson Corporation 20-26 S1C33L26 TECHNICAL MANUAL...
Page 338 = 0 (held low-level when the output data = 1). If IRTL is set to 0, a low pulse is output when the output data = 0 (held high-level when the output data = 1). Seiko Epson Corporation 20-27 S1C33L26 TECHNICAL MANUAL...
Page 339 0x0 to 0xf 0x0 R/W Register [11:8] (FSIO_ (BRTRD[11:0] = 0x0 to 0xfff) BRTRDHx) D[7:0]/FSIO_BRTRDLx, D[3:0]/FSIO_BRTRDHx BRTRD[11:0]: Baud-rate Timer Reload Data [11:0] Sets the initial counter value of the baud-rate timer. (Default: 0x0) Seiko Epson Corporation 20-28 S1C33L26 TECHNICAL MANUAL...
Page 340 At the same time a receive data buffer full interrupt request is sent to the ITC if RDBF_IE/FSIO_ INTEx register is 1. RDBF_IF is reset by writing 0. Seiko Epson Corporation 20-29 S1C33L26 TECHNICAL MANUAL...
Page 341 1 (R/W): Advanced mode 0 (R/W): Standard mode (default) The serial interface in the S1C33L26 is extended from that of the C33 STD models. The S1C33L26 se- rial interface has two operating modes, standard (STD) mode of which functions are compatible with the existing C33 STD models and an advanced (ADV) mode allowing use of the extended functions.
Page 342 21 I 21.1 S Module Overview The S1C33L26 has a built-in I S module that outputs PCM data in the I S (Inter-IC Sound) format. An audio output circuit can be simply configured by connecting external devices such as an audio DAC to the I S bus.
Page 343 Division ratio for I2S_MCLK (master clock) The I S module generates I2S_MCLK to be output from the I2S_MCLK pin by dividing the PCLK1 gener- ated by the CMU. Specify the division ratio using MCLKDIV[5:0]/I2S_DV_MCLK register. Seiko Epson Corporation 21-2 S1C33L26 TECHNICAL MANUAL...
Page 344 31 clocks 30 clocks 29 clocks 28 clocks 27 clocks 26 clocks 25 clocks 24 clocks 23 clocks 22 clocks 21 clocks 20 clocks 19 clocks 18 clocks 17 clocks 16 clocks (Default: 0x0) Seiko Epson Corporation S1C33L26 TECHNICAL MANUAL 21-3...
Page 345 Data format (MSB first/LSB first) Use DTFORM/I2S_CTL register to select either MSB first or LSB first as the data output direction. Setting DTFORM to 0 (default) selects MSB first and setting 1 selects LSB first. Seiko Epson Corporation 21-4 S1C33L26 TECHNICAL MANUAL...
Page 346 When DTTMG[1:0] is set to 0x0 (default), I S mode is selected. In this mode, the first bit of each data is output after one I2S_SCLK clock delay from the I2S_WS signal edge. Seiko Epson Corporation S1C33L26 TECHNICAL MANUAL 21-5...
Page 347 Stereo Data output Data output (Default: 0x0) The output channel mode can be switched even if data is being output. In this case, the mode changes after the current word output has finished. Seiko Epson Corporation 21-6 S1C33L26 TECHNICAL MANUAL...
Page 348 Be sure to write four stereo data (16 bits × 2 channels (L & R) × 4) to the FIFO at once in the whole empty interrupt handler, otherwise the I S module continues idle status. Seiko Epson Corporation S1C33L26 TECHNICAL MANUAL 21-7...
Page 349 Write 4 L & R data (5, 6, 7, 8) 5, 6, 7, 8 FIFO Empty 1, 2, 3, 4 2, 3, 4 3, 4 6, 7, 8 7, 8 I2S_WS pin FIFOSTAT[2:0] I2SFIFOFF I2SFIFOEF Interrupt Seiko Epson Corporation 21-8 S1C33L26 TECHNICAL MANUAL...
Page 350 When the FIFO becomes empty, I2SFIFOEF is set to 1. When data is written to the FIFO, I2SFIFOEF is reset to 0. Note, however, that the I S module continues idle status until the FIFO becomes full again. Seiko Epson Corporation S1C33L26 TECHNICAL MANUAL 21-9...
Page 351 FIFO empty occurs. If CHMD[1:0] is changed when data is be- ing output, the mode changes after the current L & R data output has finished. Seiko Epson Corporation 21-10 S1C33L26 TECHNICAL MANUAL...
Page 352 S module continues the initial status until the FIFO becomes full with four stereo data (16 bits × 2 channels (L & R) × 4). The interrupt handler should write one, two or four stereo data to the FIFO according to the inter- rupt mode selected. Seiko Epson Corporation S1C33L26 TECHNICAL MANUAL 21-11...
Page 353 R-channel output data The following describes each I S register. These are all 16-bit registers. Note: When data is written to the registers, the “Reserved” bits must always be written as 0 and not 1. Seiko Epson Corporation 21-12 S1C33L26 TECHNICAL MANUAL...
Page 354 WCLKMD = 1 I2S_WS0 (L channel) (R channel) Figure 21. 7.2 Word Clock Mode BCLKPOL: I S Output Bit Clock Polarity Select Bit Selects the bit clock polarity. 1 (R/W): Negative 0 (R/W): Positive (default) Seiko Epson Corporation S1C33L26 TECHNICAL MANUAL 21-13...
Page 355 S Output Data Timing Select Bits Selects the data bit output timing. Table 21. 7.2 Data Output Timing DTTMG[1:0] Data output timing mode Reserved Right justified mode Left justified mode S mode (Default: 0x0) Seiko Epson Corporation 21-14 S1C33L26 TECHNICAL MANUAL...
Page 356 Also in mono mode, the I2S_SDO pin is fixed at 0 during the output period for the unselected channel. The FIFO data is read out normally, therefore an interrupt occurs. Seiko Epson Corporation S1C33L26 TECHNICAL MANUAL 21-15...
Page 357 S generates the sample clock to be output from the I2S_WS pin by counting the bit clock config- ured with BCLKDIV[7:0]. Specify the half cycle (a high or low level period) of the I2S_WS clock with the number of bit clock cycles using WSCLKCYC[4:0]. Seiko Epson Corporation 21-16 S1C33L26 TECHNICAL MANUAL...
Page 358 S module generates the bit clock to be output from the I2S_SCLK pin of the I S by dividing PCLK1. Specify the division ratio using BCLKDIV[7:0]. Table 21. 7.6 I2S_SCLK (Bit Clock) Settings BCLKDIV[7:0] PCLK1 division ratio 0xff 1/512 0xfe 1/510 0xfd 1/508 (Default: 0x0) Seiko Epson Corporation S1C33L26 TECHNICAL MANUAL 21-17...
Page 359 S FIFO full flag 1 Full 0 Not full I2SFIFOEF I S FIFO empty flag 1 Empty 0 Not empty D[15:5] Reserved D[4:2] FIFOSTAT[2:0]: I S FIFO State Machine Bits Indicates the transmit FIFO status. Seiko Epson Corporation 21-18 S1C33L26 TECHNICAL MANUAL...
Page 360 WEIE S FIFO whole empty int. enable 1 Enable 0 Disable HEIE S FIFO half empty int. enable 1 Enable 0 Disable OEIE S FIFO one empty int. enable 1 Enable 0 Disable Seiko Epson Corporation S1C33L26 TECHNICAL MANUAL 21-19...
Page 361 S FIFO half empty interrupt requests to the ITC. Setting it to 0 disables in- terrupts. OEIE: I S FIFO One Empty Interrupt Enable Bit Enables or disables I S FIFO one empty interrupts. 1 (R/W): Interrupt enabled 0 (R/W): Interrupt disabled (default) Seiko Epson Corporation 21-20 S1C33L26 TECHNICAL MANUAL...
Page 362 Ch.0 starts a DMA transfer first as it priority over Ch.1. Therefore, DMAC Ch.0 must be used for L-channel data transfer. Note that 8-bit and 32-bit data transfer cannot be specified when dual DMA channels are used. Seiko Epson Corporation S1C33L26 TECHNICAL MANUAL 21-21...
Page 363 32 clocks 31 clocks 30 clocks 29 clocks 28 clocks 27 clocks 26 clocks 25 clocks 24 clocks 23 clocks 22 clocks 21 clocks 20 clocks 19 clocks 18 clocks 17 clocks 16 clocks Seiko Epson Corporation 21-22 S1C33L26 TECHNICAL MANUAL...
Page 364 The table below is made from Equitation 3 (eq3) using Excel. Table 21. 8.5 MCLKDIV[5:0] Valid Values BCLKDIV[7:0] WSCLKCYC[4:0] MCLKDIV[5:0] Results Integer Integer – Integer – – Integer – Integer – Integer – Integer – Integer – – Seiko Epson Corporation S1C33L26 TECHNICAL MANUAL 21-23...
Page 365 3 MHz (68 fs) 1.941 MHz (44 fs) 1.5 MHz (34 fs) 970.588 kHz (22 fs) 750 kHz (17 fs) Select an appropriate MCLKDIV[5:0] value according to the value listed in the above table. Seiko Epson Corporation 21-24 S1C33L26 TECHNICAL MANUAL...
Page 366 Remote Controller (REMC) 22.1 REMC Module Overview The S1C33L26 incorporates a remote controller (REMC) module for generating infrared remote control communi- cation signals. The following shows the features of the REMC module: • Supports input and output infrared remote control communication signals.
Page 367 This data length counter count clock also uses a prescaler output clock and can select one of 15 different types. The prescaler output clock is selected by LCCLK[3:0]/REMC_CFG register provided separately to the carrier genera- tion clock select bits. Seiko Epson Corporation 22-2 S1C33L26 TECHNICAL MANUAL...
Page 368 Set the data to be transmitted (High or Low) to REMDT/REMC_LCNT register. Setting REMDT to 1 outputs High; setting it to 0 outputs Low from the REMC_O pin after being modulated by the carrier signal. Seiko Epson Corporation 22-3 S1C33L26 TECHNICAL MANUAL...
Page 369 When a rising edge or falling edge interrupt occurs, write 0xff to REMLEN[7:0]/REMC_LCNT register in the interrupt handler routine to set the value to the data length counter. The data length counter starts counting down using the selected prescaler output clock from the value written. Seiko Epson Corporation 22-4 S1C33L26 TECHNICAL MANUAL...
Page 370 REMFIF/REMC_INT register to 1 within the REMC. By running the data length counter between this interrupt and a rising edge interrupt when data is being re- ceived, the received data pulse width can be calculated from that count value. Seiko Epson Corporation 22-5 S1C33L26 TECHNICAL MANUAL...
Page 371 1/2048 1/1024 1/512 1/256 (Default: 0x0) D[11:8] LCCLK[3:0]: Length Counter Clock Division Ratio Select Bits Selects a data length counter clock from the 15 prescaler (PSC Ch.1) output clocks (PCLK2 division ra- tio). Seiko Epson Corporation 22-6 S1C33L26 TECHNICAL MANUAL...
Page 372 Specify a value corresponding to the number of carrier generation clock cycles selected by CGCLK[3:0]/ REMC_CFG register + 1. Calculate carrier H section length as follows: REMCH + 1 Carrier H section length = —————— [s] clk_in REMCH: REMCH[5:0] setting clk_in: Prescaler (PSC Ch.1) output clock frequency Seiko Epson Corporation 22-7 S1C33L26 TECHNICAL MANUAL...
Page 373 – – – 0 when being read. REMFIE Falling edge interrupt enable 1 Enable 0 Disable REMRIE Rising edge interrupt enable 1 Enable 0 Disable REMUIE Underflow interrupt enable 1 Enable 0 Disable Seiko Epson Corporation 22-8 S1C33L26 TECHNICAL MANUAL...
Page 374 Enables or disables input signal rising edge interrupts. 1 (R/W): Interrupt enabled 0 (R/W): Interrupt disabled (default) REMUIE: Underflow Interrupt Enable Bit Enables or disables data length counter underflow interrupts. 1 (R/W): Interrupt enabled 0 (R/W): Interrupt disabled (default) Seiko Epson Corporation 22-9 S1C33L26 TECHNICAL MANUAL...
Page 375 Card Interface (CARD) 23.1 CARD Module Overview The S1C33L26 includes a card interface (CARD) module to connect a NAND Flash or SmartMedia cards. The following shows the features of the CARD module: • Generates the #NAND_RD and #NAND_WR signals. (Use general-purpose input/output ports to control the signals specific to NAND Flash or SmartMedia card.) •...
Page 376 I/O Ports (GPIO) 24.1 GPIO Module Overview The S1C33L26 includes general-purpose I/O ports that allow software to switch input/output direction. These share internal peripheral module input/output pins, but pins not used for peripheral modules can be used as general-pur- pose I/O ports.
Page 377 CFP91[1:0]/PMUX_P9_03 register FPDAT2 LCD_D2 SCLK0 CFP92[1:0]/PMUX_P9_03 register FPDAT3 LCD_D3 #SRDY0 CFP93[1:0]/PMUX_P9_03 register FPDAT4 LCD_D4 CFP94[1:0]/PMUX_P9_47 register FPDAT5 LCD_D5 CFP95[1:0]/PMUX_P9_47 register FPDAT6 LCD_D6 CFP96[1:0]/PMUX_P9_47 register FPDAT7 LCD_D7 CFP97[1:0]/PMUX_P9_47 register SIN1 FPDAT16 FPDAT20 CFPA0[1:0]/PMUX_PA_03 register Seiko Epson Corporation 24-2 S1C33L26 TECHNICAL MANUAL...
Page 378 PxyD is output from the port pin. The port pin outputs high level when PxyD is set to 1 and low level when set to 0. Writing to PxyD is possible without affecting pin status, even in input mode. Seiko Epson Corporation 24-3 S1C33L26 TECHNICAL MANUAL...
Page 379 0 SPT2[1:0] ANFEN SCTP2[2:0] SEPT2 SPPT2 request (to ITC) Trigger Noise Chattering SFGP2 mode/polarity filter filter SIET2 control FPT3 SPT3[1:0] ANFEN SCTP3[2:0] SEPT3 SPPT3 Trigger Noise Chattering SFGP3 mode/polarity filter filter SIET3 control Seiko Epson Corporation 24-4 S1C33L26 TECHNICAL MANUAL...
Page 380 2 SPTA[1:0] ANFEN SCTPA[2:0] SEPTA SPPTA request (to ITC) Trigger Noise Chattering SFGPA mode/polarity filter filter SIETA control FPTB SPTB[1:0] ANFEN SCTPB[2:0] SEPTB SPPTB Trigger Noise Chattering SFGPB mode/polarity filter filter SIETB control Seiko Epson Corporation 24-5 S1C33L26 TECHNICAL MANUAL...
Page 381 SPTn[1:0] setting FPT8 (SPT8[1:0]) FPT9 (SPT9[1:0]) FPTA (SPTA[1:0]) FPTB (SPTB[1:0]) 0x0 (default) Table 24. 5.4 Selecting Ports Used For Port Interrupt 3 SPTn[1:0] setting FPTC (SPTC[1:0]) FPTD (SPTD[1:0]) FPTE (SPTE[1:0]) FPTF (SPTF[1:0]) 0x0 (default) Seiko Epson Corporation 24-6 S1C33L26 TECHNICAL MANUAL...
Page 382 SIETn setting (even if the interrupt is disabled), is sent to the DMAC to trigger a DMA transfer. For more information on DMA transfer, see the “DMA Controller (DMAC)” chapter. Seiko Epson Corporation 24-7 S1C33L26 TECHNICAL MANUAL...
Page 383 Wait time = 64 × 4 / 32 = 8 [µs] The port input interrupt flag should be cleared after waiting 8 µs or more when the GPIO_ FPTnn_CHAT register is set to 0x7. Seiko Epson Corporation 24-8 S1C33L26 TECHNICAL MANUAL...
Page 384 24 I/O PORTS (GPIO) 24.6 Input Port Noise Filters The S1C33L26 provides noise filters to remove noise on the signals input from the ports shown below. USI: USI_DI, USI_CS, USI_CK USIL: USIL_DI, USIL_CS, USIL_CK FSIO: SIN0, SIN1, SCLK0, SCLK1, #SRDY0, #SRDY1...
Page 385 0x300816 PMUX_PB_03 PB[3:0] Port Function Select Register Select PB[3:0] port functions 0x300817 PMUX_PB_47 PB[7:4] Port Function Select Register Select PB[7:4] port functions 0x300818 PMUX_PC_03 PC[3:0] Port Function Select Register Select PC[3:0] port functions Seiko Epson Corporation 24-10 S1C33L26 TECHNICAL MANUAL...
Page 386 The peripheral module deter- mines whether output is enabled or disabled when the port is used for a peripheral module function. Seiko Epson Corporation 24-11 S1C33L26 TECHNICAL MANUAL...
Page 387 – – – – – – – – – – – – – Enabled – – – – – – – – – – – – – Pull-up resistors not included –: Disabled Seiko Epson Corporation 24-12 S1C33L26 TECHNICAL MANUAL...
Page 388 SPT7[1:0]: FPT7 Interrupt input Port Select Bits Selects an FPT7 port used for generating port interrupt 1. D[5:4] SPT6[1:0]: FPT6 Interrupt input Port Select Bits Selects an FPT6 port used for generating port interrupt 1. Seiko Epson Corporation 24-13 S1C33L26 TECHNICAL MANUAL...
Page 389 SPT8[1:0]: FPT8 Interrupt input Port Select Bits Selects an FPT8 port used for generating port interrupt 2. Table 24. 8.5 Selecting Ports Used For Port Interrupt 2 SPTn[1:0] setting FPT8 (SPT8[1:0]) FPT9 (SPT9[1:0]) FPTA (SPTA[1:0]) FPTB (SPTB[1:0]) 0x0 (default) Seiko Epson Corporation 24-14 S1C33L26 TECHNICAL MANUAL...
Page 390 FPTn port. When SPPTn is set to 0, low level (in level trigger mode) or falling edge (in edge trigger mode) is se- lected. Seiko Epson Corporation 24-15 S1C33L26 TECHNICAL MANUAL...
Page 391 Select Register SEPT2 FPT2 interrupt mode select 1 Edge 0 Level (GPIO_FPT03_ SEPT1 FPT1 interrupt mode select 1 Edge 0 Level MOD) SEPT0 FPT0 interrupt mode select 1 Edge 0 Level D[7:4] Reserved Seiko Epson Corporation 24-16 S1C33L26 TECHNICAL MANUAL...
Page 392 Select Register SEPTE FPTE interrupt mode select 1 Edge 0 Level (GPIO_FPTCF_ SEPTD FPTD interrupt mode select 1 Edge 0 Level MOD) SEPTC FPTC interrupt mode select 1 Edge 0 Level D[7:4] Reserved Seiko Epson Corporation 24-17 S1C33L26 TECHNICAL MANUAL...
Page 393 1 Enable 0 Disable Register SIETE FPTE interrupt enable 1 Enable 0 Disable (GPIO_FPTCF_ SIETD FPTD interrupt enable 1 Enable 0 Disable MSK) SIETC FPTC interrupt enable 1 Enable 0 Disable D[7:4] Reserved Seiko Epson Corporation 24-18 S1C33L26 TECHNICAL MANUAL...
Page 394 1 Cause of 0 Cause of R/W Reset by writing 1. Register interrupt interrupt not SFGPA FPTA interrupt flag (GPIO_FPT8B_ occurred occurred SFGP9 FPT9 interrupt flag FLG) SFGP8 FPT8 interrupt flag D[7:4] Reserved Seiko Epson Corporation 24-19 S1C33L26 TECHNICAL MANUAL...
Page 395 The FPT interrupt input ports include a chattering filter circuit for key entry that can be disabled or en- abled with a filter sampling time specified individually for each FPT port using SCTPn[2:0]. Seiko Epson Corporation 24-20 S1C33L26 TECHNICAL MANUAL...
Page 396 0x0 R/W SCTP2[2:0] time 64/f PCLK2 32/f PCLK2 16/f PCLK2 PCLK2 PCLK2 PCLK2 PCLK2 None Reserved D[6:4] SCTP3[2:0]: FPT3 Chattering Filter Time Select Bits Configures the chattering filter circuit for the FPT3 port. Seiko Epson Corporation 24-21 S1C33L26 TECHNICAL MANUAL...
Page 397 0x0 R/W SCTP6[2:0] time 64/f PCLK2 32/f PCLK2 16/f PCLK2 PCLK2 PCLK2 PCLK2 PCLK2 None Reserved D[6:4] SCTP7[2:0]: FPT7 Chattering Filter Time Select Bits Configures the chattering filter circuit for the FPT7 port. Seiko Epson Corporation 24-22 S1C33L26 TECHNICAL MANUAL...
Page 398 0x0 R/W SCTPA[2:0] time 64/f PCLK2 32/f PCLK2 16/f PCLK2 PCLK2 PCLK2 PCLK2 PCLK2 None Reserved D[6:4] SCTPB[2:0]: FPTB Chattering Filter Time Select Bits Configures the chattering filter circuit for the FPTB port. Seiko Epson Corporation 24-23 S1C33L26 TECHNICAL MANUAL...
Page 399 0x0 R/W SCTPE[2:0] time 64/f PCLK2 32/f PCLK2 16/f PCLK2 PCLK2 PCLK2 PCLK2 PCLK2 None Reserved D[6:4] SCTPF[2:0]: FPTF Chattering Filter Time Select Bits Configures the chattering filter circuit for the FPTF port. Seiko Epson Corporation 24-24 S1C33L26 TECHNICAL MANUAL...
Page 400 Wait time = 64 × 4 / 32 = 8 [µs] The port DMA function can be used after waiting 8 µs or more when the GPIO_FPTnn_ CHAT register is set to 0x7. Seiko Epson Corporation 24-25 S1C33L26 TECHNICAL MANUAL...
Page 401 0x1 (R/W): USI_DO (USI) 0x0 (R/W): P01 (GPIO) (default) D[1:0] CFP00[1:0]: P00 Port Function Select Bits 0x3 (R/W): #NAND_WR (CARD) 0x2 (R/W): SIN1 (FSIO Ch.1) 0x1 (R/W): USI_DI (USI) 0x0 (R/W): P00 (GPIO) (default) Seiko Epson Corporation 24-26 S1C33L26 TECHNICAL MANUAL...
Page 402 0x1 (R/W): SOUT0 (FSIO Ch.0) 0x0 (R/W): P05 (GPIO) (default) D[1:0] CFP04[1:0]: P04 Port Function Select Bits 0x3 (R/W): T16A_ATMA_0 (T16A5 Ch.0) 0x2 (R/W): I2S_SDO (I2S) 0x1 (R/W): SIN0 (FSIO Ch.0) 0x0 (R/W): P04 (GPIO) (default) Seiko Epson Corporation 24-27 S1C33L26 TECHNICAL MANUAL...
Page 403 0x2 (R/W): FPDAT9 (LCDC) 0x1 (R/W): USIL_DO (USIL) 0x0 (R/W): P11 (GPIO) (default) D[1:0] CFP10[1:0]: P10 Port Function Select Bits 0x3 (R/W): Reserved 0x2 (R/W): FPDAT8 (LCDC) 0x1 (R/W): USIL_DI (USIL) 0x0 (R/W): P10 (GPIO) (default) Seiko Epson Corporation 24-28 S1C33L26 TECHNICAL MANUAL...
Page 404 P20 port function select CFP20[1:0] Function 0x0 R/W reserved reserved SDCKE The GPIO pins are shared with the peripheral module pins. This register is used to select how the pins are used. D[7:4] Reserved Seiko Epson Corporation 24-29 S1C33L26 TECHNICAL MANUAL...
Page 405 0x2 (R/W): TFT_CTL1 (LCDC) 0x1 (R/W): Reserved 0x0 (R/W): P31 (GPIO) (default) D[1:0] CFP30[1:0]: P30 Port Function Select Bits 0x3 (R/W): T16A_ATMA_0 (T16A5 Ch.0) 0x2 (R/W): TFT_CTL0 (LCDC) 0x1 (R/W): Reserved 0x0 (R/W): P30 (GPIO) (default) Seiko Epson Corporation 24-30 S1C33L26 TECHNICAL MANUAL...
Page 406 P40 port function select CFP40[1:0] Function 0x0 R/W #NAND_RD FPDAT18 The GPIO pins are shared with the peripheral module pins. This register is used to select how the pins are used. D[7:6] Reserved Seiko Epson Corporation 24-31 S1C33L26 TECHNICAL MANUAL...
Page 407 0x2 (R/W): #CE5 (SRAMC) 0x1 (R/W): P52 (GPIO) 0x0 (R/W): #CE9 (SRAMC) (default) D[3:2] CFP51[1:0]: P51 Port Function Select Bits 0x3 (R/W): Reserved 0x2 (R/W): #CE4 (SRAMC) 0x1 (R/W): P51 (GPIO) 0x0 (R/W): #CE8 (SRAMC) (default) Seiko Epson Corporation 24-32 S1C33L26 TECHNICAL MANUAL...
Page 408 The GPIO pins are shared with the peripheral module pins. This register is used to select how the pins are used. D[7:2] Reserved D[1:0] CFP60[1:0]: P60 Port Function Select Bits 0x3 (R/W): #WDT_NMI (WDT) 0x2 (R/W): WDT_CLK (WDT) 0x1 (R/W): #WAIT (SRAMC) 0x0 (R/W): P60 (GPIO) (default) Seiko Epson Corporation 24-33 S1C33L26 TECHNICAL MANUAL...
Page 409 P74 port function select CFP74[1:0] Function 0x0 R/W reserved reserved AIN4 The GPIO pins are shared with the peripheral module pins. This register is used to select how the pins are used. D[7:4] Reserved Seiko Epson Corporation 24-34 S1C33L26 TECHNICAL MANUAL...
Page 410 0x2 (R/W): USIL_CK (USIL) 0x1 (R/W): FPLINE (LCDC) 0x0 (R/W): P81 (GPIO) (default) D[1:0] CFP80[1:0]: P80 Port Function Select Bits 0x3 (R/W): Reserved 0x2 (R/W): USIL_CS (USIL) 0x1 (R/W): FPFRAME (LCDC) 0x0 (R/W): P80 (GPIO) (default) Seiko Epson Corporation 24-35 S1C33L26 TECHNICAL MANUAL...
Page 411 0x1 (R/W): FPDAT1 (LCDC) 0x0 (R/W): P91 (GPIO) (default) D[1:0] CFP90[1:0]: P90 Port Function Select Bits 0x3 (R/W): SIN0 (FSIO Ch.0) 0x2 (R/W): LCD_D0 (USIL) 0x1 (R/W): FPDAT0 (LCDC) 0x0 (R/W): P90 (GPIO) (default) Seiko Epson Corporation 24-36 S1C33L26 TECHNICAL MANUAL...
Page 412 0x2 (R/W): LCD_D5 (USIL) 0x1 (R/W): FPDAT5 (LCDC) 0x0 (R/W): P95 (GPIO) (default) D[1:0] CFP94[1:0]: P94 Port Function Select Bits 0x3 (R/W): Reserved 0x2 (R/W): LCD_D4 (USIL) 0x1 (R/W): FPDAT4 (LCDC) 0x0 (R/W): P94 (GPIO) (default) Seiko Epson Corporation 24-37 S1C33L26 TECHNICAL MANUAL...
Page 413 Function 0x0 R/W Write-protected Register reserved (PMUX_PA_46) reserved #ADTRIG D3–2 CFPA5[1:0] PA5 port function select CFPA5[1:0] Function 0x0 R/W REMC_I T16A_ATMB_1 D1–0 CFPA4[1:0] PA4 port function select CFPA4[1:0] Function 0x0 R/W REMC_O T16A_ATMA_1 Seiko Epson Corporation 24-38 S1C33L26 TECHNICAL MANUAL...
Page 414 0x2 (R/W): I2S_SCLK (I2S) 0x1 (R/W): FPDAT10 (LCDC) 0x0 (R/W): PB2 (GPIO) (default) D[3:2] CFPB1[1:0]: PB1 Port Function Select Bits 0x3 (R/W): Reserved 0x2 (R/W): I2S_WS (I2S) 0x1 (R/W): FPDAT9 (LCDC) 0x0 (R/W): PB1 (GPIO) (default) Seiko Epson Corporation 24-39 S1C33L26 TECHNICAL MANUAL...
Page 415 0x2 (R/W): Reserved 0x1 (R/W): FPDAT13 (LCDC) 0x0 (R/W): PB5 (GPIO) (default) D[1:0] CFPB4[1:0]: PB4 Port Function Select Bits 0x3 (R/W): FPDAT20 (LCDC) 0x2 (R/W): Reserved 0x1 (R/W): FPDAT12 (LCDC) 0x0 (R/W): PB4 (GPIO) (default) Seiko Epson Corporation 24-40 S1C33L26 TECHNICAL MANUAL...
Page 416 0x2 (R/W): Reserved 0x1 (R/W): PC1 (GPIO) 0x0 (R/W): D9 (SRAMC) (default) D[1:0] CFPC0[1:0]: PC0 Port Function Select Bits 0x3 (R/W): Reserved 0x2 (R/W): Reserved 0x1 (R/W): PC0 (GPIO) 0x0 (R/W): D8 (SRAMC) (default) Seiko Epson Corporation 24-41 S1C33L26 TECHNICAL MANUAL...
Page 417 Enables or disables the noise filters for peripheral input ports. 1 (R/W): Enabled 0 (R/W): Disabled (default) Setting 1 to ANFEN enables the noise filters to remove noise on the signals input from the ports shown below. Seiko Epson Corporation 24-42 S1C33L26 TECHNICAL MANUAL...
Page 418 0x96. When rewriting the GPIO/PMUX registers has finished, PPROT[7:0] should be set to other than 0x96 to prevent accidental writing to the GPIO/PMUX registers. Seiko Epson Corporation 24-43 S1C33L26 TECHNICAL MANUAL...
Page 419 25 A/D CONVERTER (ADC10) A/D Converter (ADC10) 25.1 ADC10 Module Overview The S1C33L26 incorporates an A/D converter with the following features: • Conversion method: Successive approximation type • Resolution: 10 bits • Input channels: Max. 6 channels • A/D conversion clock: Max.
Page 420 • Do not start an A/D conversion when the clock output from the prescaler is turned off, and do not turn off the prescaler's clock output when an A/D conversion is underway. This may cause the A/D converter to operate erratically. Seiko Epson Corporation 25-2 S1C33L26 TECHNICAL MANUAL...
Page 421 In this case, the results that will be stored to ADD[15:0]/ADC10_ADD register is 0x0. To avoid A/D conversion for the channels without an input, set the ADCS[2:0] to equal or smaller than ADCE[2:0] within the available analog inputs. Seiko Epson Corporation 25-3 S1C33L26 TECHNICAL MANUAL...
Page 422 Writing 1 to ADCTL/ADC10_CTL register with software serves as a trigger to start A/D conversion. 25.3.5 Sampling Time Setting The analog signal input sampling time in this A/D converter is configured with ADST[2:0]/ADC10_TRG register. In the S1C33L26, do not alter ADST[2:0] from the default value (0x7). Seiko Epson Corporation 25-4 S1C33L26 TECHNICAL MANUAL...
Page 423 ADD[15:0]/ADC10_ADD register and sets the conversion completion flag ADCF/ADC10_CTL register. If mul- tiple channels are specified using ADCS[2:0]/ADC10_TRG register and ADCE[2:0]/ADC10_TRG register, the A/ D converter continues A/D conversions in the subsequent channels. Seiko Epson Corporation 25-5 S1C33L26 TECHNICAL MANUAL...
Page 424 Conversion AIN0 AIN0 A/D operation AIN0 converted data ADD[15:0] ADCF Clear Conversion result read ADOWE Interrupt request (1) Single channel (AIN0) one-time conversion mode (ADCS = 0, ADCE = 0, ADMS = 0) Seiko Epson Corporation 25-6 S1C33L26 TECHNICAL MANUAL...
Page 425 AIN0 converted data AIN1 converted data ADD[15:0] ADCF Clear Clear Conversion result read ADOWE Interrupt request (4) Multi-channel (AIN0–AIN1) continuous conversion mode (ADCS = 0, ADCE = 1, ADMS = 1) Figure 25. 4.5.1 A/D Converter Operations Seiko Epson Corporation 25-7 S1C33L26 TECHNICAL MANUAL...
Page 426 The A/D converter registers are described in detail below. These are 16-bit registers. Note: When data is written to the registers, the “Reserved” bits must always be written as 0 and not 1. Seiko Epson Corporation 25-8 S1C33L26 TECHNICAL MANUAL...
Page 427 Sets the conversion start channel with a channel number from 0 to 5. (Default: 0x0 = AIN0) STMD: Conversion Result Storing Mode Bit Selects the data alignment when the conversion results are loaded into ADD[15:0]. Seiko Epson Corporation 25-9 S1C33L26 TECHNICAL MANUAL...
Page 428 ADST[2:0] (in conversion clock cycles) 9 cycles 8 cycles 7 cycles 6 cycles 5 cycles 4 cycles 3 cycles 2 cycles (Default: 0x7) Note: Do not alter ADST[2:0] from the default value (0x7). Seiko Epson Corporation 25-10 S1C33L26 TECHNICAL MANUAL...
Page 429 An overwrite error occurs if the next A/D conversion is completed while ADCF is set (see ADOWE above), ADCF must be reset by reading ADD[15:0] before an overwrite occurs. When an overwrite er- ror occurs, ADCF is also set due to completion of conversion. Seiko Epson Corporation 25-11 S1C33L26 TECHNICAL MANUAL...
Page 430 ADC10 interrupt has occurred. • To prevent unwanted interrupts, reset ADCF and ADOWE before enabling interrupts with AD- CIE/ADC10_CTL register and ADOIE/ADC10_CTL register. Seiko Epson Corporation 25-12 S1C33L26 TECHNICAL MANUAL...
Page 431 1/16384 1/8192 1/4096 1/2048 1/1024 1/512 1/256 1/128 1/64 1/32 1/16 (Default: 0x0) Note: The A/D converter uses the prescaler output as the source clock, the prescaler must be run in ad- vance. Seiko Epson Corporation 25-13 S1C33L26 TECHNICAL MANUAL...
Page 432 26.1 LCDC Module Overview The S1C33L26 has a built-in LCD controller (LCDC) that supports 4/8-bit monochrome and color LCD panels, and 12/16/24-bit Generic HR-TFT panels. Also the S1C33L26 contains a 20K-byte VRAM (IVRAM) allowing a 320 × 240-dot 4-color/gray scale screen (2-bpp mode) to be displayed. Furthermore, the bus controller (SRAMC, SDRAMC) allows the LCDC to access the external SDRAM/SRAM as a VRAM, thus a 320 ×...
Page 433 (LUT). This consists of three tables (256 × 5 bits for red, 256 × 6 bits for green, and 256 × 5 bits for blue) and is used to set up color data to be displayed. Seiko Epson Corporation 26-2 S1C33L26 TECHNICAL MANUAL...
Page 434 FPDAT7 FPDAT8 – FPDAT9 – FPDAT10 – FPDAT11 – FPDAT12 – FPDAT13 – FPDAT14 – FPDAT15 – FPDAT16 – FPDAT17 – FPDAT18 – FPDAT19 – FPDAT20 – FPDAT21 – FPDAT22 – FPDAT23 – Seiko Epson Corporation 26-3 S1C33L26 TECHNICAL MANUAL...
Page 435 FPFRAME FPLINE FPLINE FPSHIFT DCLK FPSHIFT DCLK FPDRDY FPDRDY TFT_CTL0 TFT_CTL0 TFT_CTL1 TFT_CTL1 TFT_CTL2 TFT_CTL2 TFT_CTL3 TFT_CTL3 16-bit Generic HR-TFT LCD panel 24-bit Generic HR-TFT LCD panel Figure 26. 3.1 Typical LCD-Panel Connections Seiko Epson Corporation 26-4 S1C33L26 TECHNICAL MANUAL...
Page 436 Configuration of Display Data Memory (VRAM) The S1C33L26 has a built-in 20K-byte display data memory (IVRAM). This memory allows selection whether it is used as a VRAM by locating at 0x90000 to 0x94fff in Area 3 or a general-purpose RAM by locating in Area 0. Set- ting IVRAM_LOC/MISC_IRAM_LOC register to 0 configures the IVRAM as a general-purpose RAM in Area 0;...
Page 437 This clock is required for the LCDC to access the VRAM. BCLK can be stopped in HALT mode using BCLK_ EN/CMU_CLKCTL register. PCLK2 This clock is required for accessing the LCDC registers. PCLK2 can be stopped using PCLK2_EN/CMU_ CLKCTL register. Seiko Epson Corporation 26-6 S1C33L26 TECHNICAL MANUAL...
Page 438 STN Panel Timing Parameters The STN panel timing parameters shown in Figures below can be set using the LCDC control registers. Display period Non display period Figure 26. 5.2.1 STN Panel Timing Parameters Seiko Epson Corporation 26-7 S1C33L26 TECHNICAL MANUAL...
Page 439 * Diagram drawn with 2 FPLINE vertical blank period Example timing for a 320 × 240 panel For this timing diagram FPSMASK is set to 1 Figure 26. 5.2.3 8-bit Single Monochrome Panel Timing Chart (Example) Seiko Epson Corporation 26-8 S1C33L26 TECHNICAL MANUAL...
Page 440 1-G11 1-G16 1-B16 1-B240 * Diagram drawn with 2 FPLINE vertical blank period Example timing for a 320 × 240 panel Figure 26. 5.2.5 8-bit Single Color Panel (Format 1) Timing Chart (Example) Seiko Epson Corporation 26-9 S1C33L26 TECHNICAL MANUAL...
Page 441 Use VDPCNT[9:0]/LCDC_VDISP register to set the vertical display period (= vertical panel resolution). VDP = VDPCNT[9:0] + 1 [lines] VDPCNT[9:0] must be programmed such that the following condition is met: VT ≥ VDP + 1 Seiko Epson Corporation 26-10 S1C33L26 TECHNICAL MANUAL...
Page 442 FPDAT[23:0] D319 D320 FPDRDY (DEN) TFT_CTL3 (SPL) TFT_CTL1 pulse start offset TFT_CTL1 (CLS) TFT_CTL1 pulse stop offset TFT_CTL0 pulse start offset TFT_CTL0 (PS) TFT_CTL0 pulse stop offset TFT_CTL2 delay TFT_CTL2 (REV) Horizontal timing Seiko Epson Corporation 26-11 S1C33L26 TECHNICAL MANUAL...
Page 443 VT: Vertical total period Use VTCNT[9:0]/LCDC_VDISP register to set the vertical total period. VT = VTCNT[9:0] + 1 [lines] VTCNT[9:0] must be programmed such that the following condition is met: VT > VDP + VDPS Seiko Epson Corporation 26-12 S1C33L26 TECHNICAL MANUAL...
Page 444 When HR-TFT panel is selected (PANELSEL/LCDC_DISPMOD register = 1), the FPSHIFT (DCLK) clock does not stop even in the horizontal non-display period by the default setting. To stop the FPSHIFT clock dur- ing the horizontal non-display period, set FPSHIFT_MSK/LCDC_DISPMOD register to 1. Seiko Epson Corporation 26-13 S1C33L26 TECHNICAL MANUAL...
Page 445 LUTRAM * CSTN panel Color Bypass Color LUTRAM * MSTN panel Monochrome Bypass Monochrome MLUT * To use LUTRAM, DSTRAM_CFG/MISC_RAM_LOC register must be set to 1. However, set it to 0 when rewriting LUTRAM. Seiko Epson Corporation 26-14 S1C33L26 TECHNICAL MANUAL...
Page 446 Each byte begins with the MSB and byte data are aligned in little-endian format. Color pixel data begins with Red bits, then Green and Blue bits follow. Seiko Epson Corporation 26-15 S1C33L26 TECHNICAL MANUAL...
Page 447 MSB LSB FPDAT signals D1 D0 When LUT is used LUT entry number FPDAT signals entries 0 to 3 Brightness data in the specified entry Figure 26. 5.5.3 VRAM Data Format in 2-bpp Mode Seiko Epson Corporation 26-16 S1C33L26 TECHNICAL MANUAL...
Page 448 0x76 0x54 0x32 0x10 ..0x1000 0140 0x89 0xab 0xcd 0xef ..Note) Display may be inverted depending on the LCD panel used. Figure 26. 5.5.6 Example of VRAM Data in 4-bpp Mode Seiko Epson Corporation 26-17 S1C33L26 TECHNICAL MANUAL...
Page 449 R3 R2 R1 R0 G3 G2 G1 G0 Byte 1 FPDAT signals B3 B2 B1 B0 R3 R2 R1 R0 Byte 0 G3 G2 G1 G0 B3 B2 B1 B0 Even pixel Figure 26.5.5.9 VRAM Data Format in 12-bpp Mode Seiko Epson Corporation 26-18 S1C33L26 TECHNICAL MANUAL...
Page 450 Note) Display may be inverted depending on the LCD panel used. Figure 26. 5.5.12 Example of VRAM Data in 16-bpp Mode Note: The LCDC supports up to 4K colors for CSTN panels even if 16-bpp mode is selected. Seiko Epson Corporation 26-19 S1C33L26 TECHNICAL MANUAL...
Page 451 The following shows the relationship between pixel data and FPDAT signals in each bpp mode: Note: The signal levels described in this section assume that SWINV/LCDC_DISPMOD register is set to 0. They will be inverted if SWINV is set to 1 (software inverse video enabled). Seiko Epson Corporation 26-20 S1C33L26 TECHNICAL MANUAL...
Page 452 To ensure a uniform brightness, D3 to D0 are connected to the TFT panel RGB signals repeatedly. 4-bpp pixel data LCDC signals TFT panel TFT panel TFT panel R signals G signals B signals Figure 26. 5.6.3 FPDAT Signals in LUT Bypass Mode (TFT panel, 4-bpp mode) Seiko Epson Corporation 26-21 S1C33L26 TECHNICAL MANUAL...
Page 453 FPDAT2 = Low (0) FPDAT12 = Low (0) FPDAT7 = High (1) FPDAT1 = High (1) FPDAT11 = High (1) FPDAT6 = High (1) FPDAT0 = Low (0) FPDAT5 = Low (0) FPDAT[23:16] = Low (0) Seiko Epson Corporation 26-22 S1C33L26 TECHNICAL MANUAL...
Page 454 FPDAT2 = High (1) FPDAT12 = High (1) FPDAT7 = Low (0) FPDAT1 = High (1) FPDAT11 = High (1) FPDAT6 = Low (0) FPDAT0 = High (1) FPDAT5 = High (1) FPDAT[23:16] = Low (0) Seiko Epson Corporation 26-23 S1C33L26 TECHNICAL MANUAL...
Page 455 FPDAT[7:4] (4-bit passive panel) G brightness of the FPDAT signal FPDAT[7:0] (8-bit passive panel) B brightness of the FPDAT signal Figure 26. 5.6.9 FPDAT Signals in LUT Bypass Mode (CSTN panel, 2-bpp mode) Seiko Epson Corporation 26-24 S1C33L26 TECHNICAL MANUAL...
Page 456 5.6.14 FPDAT Signals in LUT Bypass Mode (MSTN panel, 1-bpp mode) 2-bpp mode (MSTN panel, LUT bypassed) 2-bpp pixel data Brightness of the FPDAT signal Figure 26. 5.6.15 FPDAT Signals in LUT Bypass Mode (MSTN panel, 2-bpp mode) Seiko Epson Corporation 26-25 S1C33L26 TECHNICAL MANUAL...
Page 457 DAT signals are generated based on the color or gray level stored in the LUT entry indicated by the VRAM data, before being output to the LCD panel. The S1C33L26 includes two different look-up tables, LUTRAM for color mode and MLUT for monochrome mode.
Page 458 Setting data to the monochrome look-up table Use the monochrome look-up table data registers for writing and reading 4-bit gray scale data to/from the look-up table. The monochrome look-up table data registers are mapped to addresses 0x302090 and 0x302094. Seiko Epson Corporation 26-27 S1C33L26 TECHNICAL MANUAL...
Page 459 This setup item is provided for EL panels. Whether the frame-rate modulation pattern is to be repeated every 0x40000 frames (counted by the internal frame counter) can be set using FRMRPT/LCDC_DISPMOD register. FRMRPT = 1: FRM pattern repeated (for EL panel) FRMRPT = 0: FRM pattern not repeated (default) Seiko Epson Corporation 26-28 S1C33L26 TECHNICAL MANUAL...
Page 460 LCD panel. Note that a word boundary address (A[1:0] = 0b00) in IVRAM or the external VRAM must be specified to this register. Main screen address offset for virtual screen The S1C33L26 LCDC supports a virtual screen feature to use the VRAM with a different size from that of the LCD panel. Seiko Epson Corporation...
Page 461 Display area 1st line 0x10012ca0– 0x10012ca0 2nd line 0x10012f20– 3rd line 0x100131a0– 240th line 0x10038220– (479, 359) 40 words 80 words Screen address offset 160 words Figure 26. 6.2.2 Example of Virtual Screen Configuration Seiko Epson Corporation 26-30 S1C33L26 TECHNICAL MANUAL...
Page 462 The sub-window width must be a multiple of (32 bits ÷ bpp). Sub-window coordinates The display position and size of the sub-window are configured with the X and Y coordinates of the start posi- tion (upper left corner) and end position (lower right corner). Seiko Epson Corporation 26-31 S1C33L26 TECHNICAL MANUAL...
Page 463 • Virtual sub-screen size: such as 1024 × 768 pixels can also be configured.) 160 × 120 pixels • Sub-window size: • Sub-window start position: X = 80 pixels, Y = 60 pixels Seiko Epson Corporation 26-32 S1C33L26 TECHNICAL MANUAL...
Page 464 PIP_XEND[9:0] = (80 + 160) pixels × 4 bpp ÷ 32 bits - 1 = 29 words = 0x1d PIP_YEND[9:0] = 60 + 120 lines - 1 = 179 lines = 0xb3 LCDC_SUBEP register = 0x00b3001d Seiko Epson Corporation 26-33 S1C33L26 TECHNICAL MANUAL...
Page 465 All operations of the LCD controller, other than accessing of its control registers and look-up tables are disabled. The LCD controller is placed in power-save mode by setting PSAVE[1:0] to 0x0. The LCD controller is taken out of power-save mode by setting PSAVE[1:0] to 0x3. Seiko Epson Corporation 26-34 S1C33L26 TECHNICAL MANUAL...
Page 466 0 when the reloading is completed. LUT reload function The LUT reload function is used to replace the look-up table settings. This function is effective when the look- up table function is enabled (LUTPASS/LCDC_DISPMOD = 0). Seiko Epson Corporation 26-35 S1C33L26 TECHNICAL MANUAL...
Page 467 Monochrome Look-up Table Register 0 Monochrome look-up table data entries 0–7 0x302094 LCDC_MLUT1 Monochrome Look-up Table Register 1 Monochrome look-up table data entries 8–15 The LCDC registers are described in detail below. These are 32-bit registers. Seiko Epson Corporation 26-36 S1C33L26 TECHNICAL MANUAL...
Page 468 D[6:2] Reserved D[1:0] PSAVE[1:0]: Power Save Mode Select Bits Selects the power-save mode. Table 26. 10.2 Power-Save Mode Settings PSAVE[1:0] Mode Normal operation Reserved Reserved Power-save mode (Default: 0x0) Seiko Epson Corporation 26-37 S1C33L26 TECHNICAL MANUAL...
Page 469 Sets the vertical total period (VT) in line units. (Default: 0x0) VT = VTCNT[9:0] + 1 [lines] The vertical total period contains vertical display period and vertical non-display period and the maxi- mum value that can be set is 1,024 lines. Seiko Epson Corporation 26-38 S1C33L26 TECHNICAL MANUAL...
Page 470 TFT STN panels. (LCDC_VDPS) VT > VDP + VDPS Note: This register is used only for setting HR-TFT panel parameters. When using an STN panel, leave this register unaltered as 0x0. D[31:10] Reserved Seiko Epson Corporation 26-39 S1C33L26 TECHNICAL MANUAL...
Page 471 D[25:16] FPFRAME_ST[9:0]: FPFRAME Pulse Start Position Setup Bits Sets the vertical sync pulse (FPFRAME or SPS) start position (VPS) for HR-TFT panels. (Default: 0x0) VPS = FPFRAME_ST[9:0] [lines] = FPFRAME_ST[9:0] × HT [Ts] (Ts: pixel clock period) D[15:8] Reserved Seiko Epson Corporation 26-40 S1C33L26 TECHNICAL MANUAL...
Page 472 LCDC_TFT_CTL1 register or preset with standard conditions. CTL1CTL is set to 0 by default, in this case the TFT_CTL1 (CLS) signal toggles between high and low every time the FPLINE (LP) pulse is output. Seiko Epson Corporation 26-41 S1C33L26 TECHNICAL MANUAL...
Page 473 FPLINE pulse start position. (Default: 0x0) Setting this register configures the TFT_CTL1 pulse width to “CTL1STP[9:0] - CTL1ST[9:0] + 1 [Ts].” To enable this register, set CTL1CTL/LCDC_TFTSO register and CTLCNT_RUN/LCDC_TFTSO reg- ister to 1. Seiko Epson Corporation 26-42 S1C33L26 TECHNICAL MANUAL...
Page 474 Reserved LUTRLD: LUT Reload Trigger Bit Replaces the look-up table values by the reload table data. 1 (W): Trigger to reload 0 (W): Ignored 1 (R): Reloading 0 (R): Reloading has finished (default) Seiko Epson Corporation 26-43 S1C33L26 TECHNICAL MANUAL...
Page 475 A 1K-byte boundary address in IVRAM or an external memory must be specified. Note: DSTRAM in Area 3 cannot be used to locate the reload table. For more information, see “Bus Masters and Accessible Memories” in the “Memory Map” chapter. D[9:0] Reserved Seiko Epson Corporation 26-44 S1C33L26 TECHNICAL MANUAL...
Page 476 Color single 8-bit passive LCD panel (format 1) Color single 4-bit passive LCD panel Monochrome single 8-bit passive LCD panel Reserved Monochrome single 8-bit passive LCD panel Monochrome single 4-bit passive LCD panel Seiko Epson Corporation 26-45 S1C33L26 TECHNICAL MANUAL...
Page 477 BPP[2:0]: Bit-Per-Pixel Select Bits Selects the bpp mode. Table 26. 10.4 Specification of Bpp Mode BPP[2:0] bpp mode Reserved 24 bpp 16 bpp 12 bpp 8 bpp 4 bpp 2 bpp 1 bpp (Default: 0x0) Seiko Epson Corporation 26-46 S1C33L26 TECHNICAL MANUAL...
Page 478 The set value is calculated as follows: SW_OFS[11:0] = virtual screen width in pixels × bpp / 32 See “Main screen address offset for virtual screen” in Section 26.6.2 for more information on the virtual screen and the configurations. Seiko Epson Corporation 26-47 S1C33L26 TECHNICAL MANUAL...
Page 479 D15–10 – reserved – – – 0 when being read. D9–0 PIP_XEND Sub-window horizontal (X) end X end position = PIP_XEND 0x0 R/W (*3) [9:0] position (pixels) from the origin (word units) D[31:26] Reserved Seiko Epson Corporation 26-48 S1C33L26 TECHNICAL MANUAL...
Page 480 4-bpp mode: All entries are used. D[31:28], D[27:24], D[23:20], D[19:16], D[15:12], D[11:8], D[7:4], D[3:0] MLUTn[3:0]: Monochrome LUT Entry n Data Bits Sets the 4-bit data for the monochrome look-up table entry n. (Default: 0x0) Seiko Epson Corporation 26-49 S1C33L26 TECHNICAL MANUAL...
Page 481 27.1 GE Module Overview The S1C33L26 includes a graphics engine (GE) for drawing basic objects (e.g., straight lines, rectangles, circles) and bitmap texts with a specified font on a VRAM. The GE provides drawing commands in which drawing effects such as clipping, line width setting, octant selection for circle drawing, block copy, XOR/mesh/transparency, color replacement/color inversion with palettes, and resize/tiling/rotation in 90-degree angle (texts/compressed image) can be specified as well as shape and color.
Page 482 The work area is configured with coordinate values specified using VWIN_W[11:0]/GE_WK_SIZE register for width and VWIN_H[11:0]/GE_WK_SIZE register for height. Work area width: VWIN_W[11:0] + 1 (pixels) Work area height: VWIN_H[11:0] + 1 (pixels) Effective coordinate values: (0, 0) to (VWIN_W[11:0], VWIN_H[11:0]) Seiko Epson Corporation 27-2 S1C33L26 TECHNICAL MANUAL...
Page 483 The embedded LCDC module supports a virtual screen function to use an image area larger than the LCD panel size. Any location in the virtual screen area can be displayed on the LCD panel. This allows multiple- screens to be configured in the VRAM and panning/scrolling large images. Seiko Epson Corporation 27-3 S1C33L26 TECHNICAL MANUAL...
Page 484 Drawing to outside the clipping area is masked even if it is within the work area. Seiko Epson Corporation 27-4 S1C33L26 TECHNICAL MANUAL...
Page 485 This section introduces the objects that can be drawn using the drawing commands. The drawing commands also allow drawing effect specifications such as clipping and transparency (see Section 27.3.5). Dot drawing / DOT command (0x10) Fills the pixel at the X and Y coordinates specified with the specified color. Seiko Epson Corporation 27-5 S1C33L26 TECHNICAL MANUAL...
Page 486 When an even number is specified as the line width, the left or upper side from the specified axis will be thicker by one pixel than the right or lower side. Seiko Epson Corporation 27-6 S1C33L26 TECHNICAL MANUAL...
Page 487 Figure 27. 3.2.6 Drawing Solid Filled Rectangle Solid filled quadrilateral drawing / QUAD_FILL command (0x18) Draws a solid filled quadrilateral specified with the X and Y coordinates of the four vertices, and a color. Seiko Epson Corporation 27-7 S1C33L26 TECHNICAL MANUAL...
Page 488 (0, 0) Arc selections (1/8 Position Select) (X, Y) Width 0x10 0x80 0x20 0x40 Examples: (Clipping area) 0x10 0x20 0x40 0x80 Work area 0x3f 0x11 0x33 0x55 0x6f 0xff Figure 27. 3.2.9 Circle Drawing Seiko Epson Corporation 27-8 S1C33L26 TECHNICAL MANUAL...
Page 489 (24 bytes in this example) Font base address is the start address of the first character data. The font header is not started from the font base address. Figure 27. 3.3.1 Font Data Format Seiko Epson Corporation 27-9 S1C33L26 TECHNICAL MANUAL...
Page 490 (X2, Y2) (Clipping area) Work area Memory Normal Rotation Resizing Tiling (X1, Y1) (X1, Y1) (X1, Y1) (X1, Y1) (X2, Y2) (X2, Y2) (X2, Y2) (X2, Y2) Figure 27. 3.4.1 Decompression and Drawing Seiko Epson Corporation 27-10 S1C33L26 TECHNICAL MANUAL...
Page 491 The GE module uses one of the two color conversion tables (CCT and CCT1) for this conversion. bcTable bcTable = 1 Image data Color depth conversion CCT1 (16 + 4 + 2 bytes) Figure 27. 3.4.3 Configuration of Color Conversion Tables Seiko Epson Corporation 27-11 S1C33L26 TECHNICAL MANUAL...
Page 492 8 and 16 bpp image data do not support color depth conversion and are extended without color conversion. The bcTable bit is ignored and the data header cannot contain CCT. An un- expected drawing will result if CCT exists in 8 or 16 bpp image data . Seiko Epson Corporation 27-12 S1C33L26 TECHNICAL MANUAL...
Page 493 The USIL transmit data buffer address should be specified as the destination. (0, 0) Memory (X1, Y1) Image data (X2, Y2) USIL Parallel I/F Built-in RAM Transmit or SPI LCD driver/panel data buffer Work area Figure 27. 3.4.6 Image Data Block Transfer Seiko Epson Corporation 27-13 S1C33L26 TECHNICAL MANUAL...
Page 494 The transparent color must be set to MAGIC_COL[15:0]/GE_MAGIC register in advance. A color within the effective range for the bpp mode (set using DISP_BPP[2:0]/GE_DISP_CFG register) can only be specified. Note that transparent color comparison is performed with the pixel color after being converted via CCT. Seiko Epson Corporation 27-14 S1C33L26 TECHNICAL MANUAL...
Page 495 The mesh pattern is configured using MESH_RW[1:0]/GE_MESH register for specifying the horizontal line width and MESH_CW[1:0]/GE_MESH register for specifying the vertical line width. Table 27. 3.5.3 Mesh Pattern Settings MESH_RW[1:0]/MESH_CW[1:0] Mesh size 4 pixels Reserved 2 pixels 1 pixel (Default: 0x0) Seiko Epson Corporation 27-15 S1C33L26 TECHNICAL MANUAL...
Page 496 Palette Select[1:0] bits to select the palette to be used. When the Palette Select[1:0] bits are set to 0x0, no palette is used and the original color data is written to the work area through the writing effect specified. Seiko Epson Corporation 27-16 S1C33L26 TECHNICAL MANUAL...
Page 497 The circle command and the solid filled circle command allow selection of one or more arcs and circular sec- tions to be drawn from eight locations split by 45° using the 1/8 Position Select[7:0] bits. Seiko Epson Corporation 27-17 S1C33L26 TECHNICAL MANUAL...
Page 498 A drawing area with a different horizontal to vertical ratio can be specified. (0, 0) (X1, Y1) (X1, Y1) Original character/image (X2, Y2) (X2, Y2) Work area Memory Figure 27. 3.5.7 Resizing Characters/Images Seiko Epson Corporation 27-18 S1C33L26 TECHNICAL MANUAL...
Page 499 *1: Data is transferred to the built-in RAM LCD driver/panel via USIL set to LCD SPI mode or LCD parallel I/F mode. Specify the USIL transmit data buffer address as the destination. *2: IVRAM (Area 3) or an external memory located in Areas 13 to 22 Seiko Epson Corporation 27-19 S1C33L26 TECHNICAL MANUAL...
Page 500 The GE_CMD_ADDR register contents are updated by fetching each command. Terminating execution Termination by a STOP command The GE command stops executing a command list when it executes a STOP command (STOP1 to STOP4). Seiko Epson Corporation 27-20 S1C33L26 TECHNICAL MANUAL...
Page 501 Note: BUS_STS is set after lapse of 3 cycles from a trigger by GE_RUN. To avoid reading undefined BUS_STS, insert three or more “nop” instructions after setting GE_RUN to 1. Seiko Epson Corporation 27-21 S1C33L26 TECHNICAL MANUAL...
Page 502 ERR[3:0]/GE_IF1 register. A calculation error interrupt can be generated at this point. Read CALC_ERR[3:0] in the interrupt handler routine to identify the error that occurred. The CALC_ERR[3:0] bits that have been set are cleared by writing 0x0 or 0xff in byte to address 0x302448. Seiko Epson Corporation 27-22 S1C33L26 TECHNICAL MANUAL...
Page 503 (GE_ERR_IE1 = 1). 0b0100 Color depth over The specified drawing color or a pixel color in the image data is out of the effective range for the bpp mode set in the GE. Seiko Epson Corporation 27-23 S1C33L26 TECHNICAL MANUAL...
Page 504 After a cold reset, all the information must be reset. Follow the procedure shown below to perform a cold reset. START GE_HRST ← 1 DRAW_STS = 0? BUS_STS = 0? GE_CRST ← 1 Figure 27. 4.6.1 Cold Reset Flow Seiko Epson Corporation 27-24 S1C33L26 TECHNICAL MANUAL...
Page 505 (at the end of command list) Not occurred Not occurred End-of-execution interrupt Completed Occurred Occurred/ Calculation error interrupt Stopped Not occurred Not occurred Occurred/ End-of-execution interrupt Completed Not occurred (at the end of command list) Seiko Epson Corporation 27-25 S1C33L26 TECHNICAL MANUAL...
Page 506 • The command must begin from a word (32-bit) boundary address. • Command lists must be programmed in IVRAM (Area 3) or an external memory located in Ar- eas 13 to 22. IRAM (Area 0) cannot be used to execute command lists. Seiko Epson Corporation 27-26 S1C33L26 TECHNICAL MANUAL...
Page 507 There is no difference on the stop function of STOP1 to STOP4. However, by reading EXE_END[2:0]/GE_IF3 register after an end-of-execution interrupt has occurred, the STOP (STOP1 to STOP4) command (or the cause of termination), which has stopped command execution, can be identified. Seiko Epson Corporation 27-27 S1C33L26 TECHNICAL MANUAL...
Page 508 D[21:20] Palette Select[1:0] Bits Selects the palette to be used when converting colors with a palette. (See Section 27.3.5.) Table 27. 5.5.1 Palette Selection Palette Select[1:0] bits Palette Palette 3 Palette 2 Palette 1 Not used Seiko Epson Corporation 27-28 S1C33L26 TECHNICAL MANUAL...
Page 509 Specifies the Y coordinate of the dot to be drawn. D[15:0] X Coordinate[15:0] Bits Specifies the X coordinate of the dot to be drawn. (0, 0) (X, Y) (Clipping area) Work area Figure 27. 5.5.1 Dot Drawing Seiko Epson Corporation 27-29 S1C33L26 TECHNICAL MANUAL...
Page 510 5.6.2 Writing Effect Selections Write Effect Setting[2:0] bits Writing effect 0x7–0x4 Reserved Rewrite Mesh Normal (Fill) D[15:0] Color[15:0] Bits Specifies the drawing color. The effective bits depend on the GE bpp mode (set using DISP_BPP[2:0]/GE_DISP_CFG register). Seiko Epson Corporation 27-30 S1C33L26 TECHNICAL MANUAL...
Page 511 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 0x12 0xffff Effect Setting ARG1 Color reserved ARG2 reserved Line Width ARG3 Y1 Coordinate X1 Coordinate ARG4 Y2 Coordinate X2 Coordinate Seiko Epson Corporation 27-31 S1C33L26 TECHNICAL MANUAL...
Page 512 The color data may be modified before being written to the work area according to the palette and/or writing effect settings. (See Section 27.3.5.) Argument 2 (Line width) D[31:12] Reserved D[11:0] Line Width[11:0] Bits Specifies the line width in number of pixels. (See Section 27.3.2.) Seiko Epson Corporation 27-32 S1C33L26 TECHNICAL MANUAL...
Page 513 Clip Enable Bit Enables or disables the clipping function. (See Section 27.3.5.) 1: Clipping enabled 0: Clipping disabled Transparent Enable Bit Enables or disables transparency. (See Section 27.3.5.) 1: Transparency enabled 0: Transparency disabled Seiko Epson Corporation 27-33 S1C33L26 TECHNICAL MANUAL...
Page 514 Specifies the X coordinate of the 2nd vertex. Argument 4 (Coordinates of 3rd vertex) D[31:16] Y3 Coordinate[15:0] Bits Specifies the Y coordinate of the 3rd vertex. D[15:0] X3 Coordinate[15:0] Bits Specifies the X coordinate of the 3rd vertex. Seiko Epson Corporation 27-34 S1C33L26 TECHNICAL MANUAL...
Page 515 D[21:20] Palette Select[1:0] Bits Selects the palette to be used when converting colors with a palette. (See Section 27.3.5.) Table 27. 5.9.1 Palette Selection Palette Select[1:0] bits Palette Palette 3 Palette 2 Palette 1 Not used Seiko Epson Corporation 27-35 S1C33L26 TECHNICAL MANUAL...
Page 516 Specifies the Y coordinate of the lower right corner. D[15:0] X2 Coordinate[15:0] Bits Specifies the X coordinate of the lower right corner. (0, 0) (X1, Y1) (X2, Y2) (Clipping area) Work area Figure 27. 5.9.1 Drawing Solid Filled Rectangle Seiko Epson Corporation 27-36 S1C33L26 TECHNICAL MANUAL...
Page 517 5.10.2 Writing Effect Selections Write Effect Setting[2:0] bits Writing effect 0x7–0x4 Reserved Rewrite Mesh Normal (Fill) D[15:0] Color[15:0] Bits Specifies the drawing color. The effective bits depend on the GE bpp mode (set using DISP_BPP[2:0]/GE_DISP_CFG register). Seiko Epson Corporation 27-37 S1C33L26 TECHNICAL MANUAL...
Page 518 (0, 0) (X2, Y2) (X1, Y1) (X4, Y4) (X3, Y3) (Clipping area) Work area Figure 27. 5.10.1 Drawing Solid Filled Quadrilateral Seiko Epson Corporation 27-38 S1C33L26 TECHNICAL MANUAL...
Page 519 5.11.1 Palette Selection Palette Select[1:0] bits Palette Palette 3 Palette 2 Palette 1 Not used Sync Enable Bit Enables or disables the LCDC synchronization function. (See Section 27.3.5.) 1: Enabled (Synchronized) 0: Disabled (Not synchronized) Seiko Epson Corporation 27-39 S1C33L26 TECHNICAL MANUAL...
Page 520 D[31:16] Y Coordinate[15:0] Bits Specifies the Y coordinate of the center. D[15:0] X Coordinate[15:0] Bits Specifies the X coordinate of the center. (0, 0) (X, Y) Width (Clipping area) Work area Figure 27. 5.11.2 Circle Drawing Seiko Epson Corporation 27-40 S1C33L26 TECHNICAL MANUAL...
Page 521 5.12.1 Palette Selection Palette Select[1:0] bits Palette Palette 3 Palette 2 Palette 1 Not used Sync Enable Bit Enables or disables the LCDC synchronization function. (See Section 27.3.5.) 1: Enabled (Synchronized) 0: Disabled (Not synchronized) Seiko Epson Corporation 27-41 S1C33L26 TECHNICAL MANUAL...
Page 522 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 0x20 0xffff ARG1 reserved Font Index Offset Height Width ARG2 Character Color Background color ARG3 Font Set Base Address Seiko Epson Corporation 27-42 S1C33L26 TECHNICAL MANUAL...
Page 523 The CHAR command draws a character or symbol specified by an index in the character set at the specified loca- tion. The command also allows specification of drawing effects such as resizing, tiling, and rotation as well as gen- eral drawing effects. Seiko Epson Corporation 27-43 S1C33L26 TECHNICAL MANUAL...
Page 524 Font Index[15:0] Bits Specifies the character to be drawn with the index in the font set. The first character is specified as index 0 and the subsequent character indexes are incremented by char- acter. Seiko Epson Corporation 27-44 S1C33L26 TECHNICAL MANUAL...
Page 525 If the image data has a color depth (1/2/4 bpp) different from the bpp mode set in the GE module, the color data is automatically converted according to the GE bpp mode before the image is written to the work area (color reduc- tion is not supported). Seiko Epson Corporation 27-45 S1C33L26 TECHNICAL MANUAL...
Page 526 0: Disabled (Not synchronized) D[18:16] Write Effect Setting[2:0] Bits Selects a writing effect. (See Section 27.3.5.) Table 27. 5.15.4 Writing Effect Selections Write Effect Setting[2:0] bits Writing effect 0x7–0x3 Reserved Mesh Normal (Fill) D[15:0] Reserved Seiko Epson Corporation 27-46 S1C33L26 TECHNICAL MANUAL...
Page 527 Draw- ing effects such as clipping and transparency that apply to the destination can also be specified. Seiko Epson Corporation 27-47 S1C33L26 TECHNICAL MANUAL...
Page 528 Specifies the X coordinate of the transfer source area lower right corner. Argument 4 (Coordinates of transfer destination area upper left corner) D[31:16] Destination Y1 Coordinate[15:0] Bits Specifies the Y coordinate of the transfer destination area upper left corner. Seiko Epson Corporation 27-48 S1C33L26 TECHNICAL MANUAL...
Page 529 *1: Data is transferred to the built-in RAM LCD driver/panel via USIL set to LCD SPI mode or LCD paral- lel I/F mode. Specify the USIL transmit data buffer address as the destination. *2: IVRAM (Area 3) or an external memory located in Areas 13 to 22 D[25:23] Reserved Seiko Epson Corporation 27-49 S1C33L26 TECHNICAL MANUAL...
Page 530 D[31:16] Y2 Coordinate[15:0] Bits Specifies the Y coordinate of the transfer area lower right corner (within work area). D[15:0] X2 Coordinate[15:0] Bits Specifies the X coordinate of the transfer area lower right corner (within work area). Seiko Epson Corporation 27-50 S1C33L26 TECHNICAL MANUAL...
Page 531 The command start address must be a word boundary address in Areas 3–5, 7–10, 13–16, and 19–22. The low-order 2 bits are always fixed at 0. The address in this register is incremented by the size of the command executed indicating the command address to be subsequently executed. Seiko Epson Corporation 27-51 S1C33L26 TECHNICAL MANUAL...
Page 532 1 (R): Running 0 (R): Stopped (default) DRAW_STS is set to 1 when the GE starts writing to the work area (VRAM) and is reset to 0 after the writing has finished. D[7:4] Reserved Seiko Epson Corporation 27-52 S1C33L26 TECHNICAL MANUAL...
Page 533 Calculation error interrupt enable 1 Enable 0 Disable D[31:17] Reserved GE_END_IE: GE End-of-Execution Interrupt Enable Bit Enables or disables interrupts caused by termination of command execution. 1 (R/W): Interrupt enabled 0 (R/W): Interrupt disabled (default) Seiko Epson Corporation 27-53 S1C33L26 TECHNICAL MANUAL...
Page 534 Trace width An illegal line width (less than 1 or a value that exceeds the object size) is specified in a object (line) drawing command. No error No error has occurred. Seiko Epson Corporation 27-54 S1C33L26 TECHNICAL MANUAL...
Page 535 When DRAW_ERR3 is set to 1, a drawing error interrupt request is output to the ITC if GE_ERR_IE0 has been set to 1 (interrupt enabled). An interrupt is generated if the ITC and C33 PE Core interrupt conditions are satisfied. Seiko Epson Corporation 27-55 S1C33L26 TECHNICAL MANUAL...
Page 536 1 (interrupt enabled). An interrupt is generated if the ITC and C33 PE Core interrupt conditions are satisfied. DRAW_ERR0 is reset by writing 1. The GE does not stop command execution even if this error has occurred. Seiko Epson Corporation 27-56 S1C33L26 TECHNICAL MANUAL...
Page 537 (Cannot be altered.) D[31:0] VWIN_ADDR[31:0]: Work Area Start Address Bits Specifies the memory address from which the work area begins. (Default: 0x0) The work area start address must be a 1K-byte boundary address. Seiko Epson Corporation 27-57 S1C33L26 TECHNICAL MANUAL...
Page 538 D[31:17] Reserved TF_TYPE: Block Transfer Type Select Bit Selects the transfer data type for block transfer from the work area to USIL. 1 (R/W): Pixel to Byte 0 (R/W): Byte to Byte (default) Seiko Epson Corporation 27-58 S1C33L26 TECHNICAL MANUAL...
Page 539 When LCDC synchronization function is disabled, the GE draws objects/images without a delay. In this case, the SYNC_TYPE setting is ineffective. Reserved D[2:0] DISP_BPP[2:0]: Color Depth Bits Selects the color depth (bpp mode) of image data to be written to the work area (VRAM). Seiko Epson Corporation 27-59 S1C33L26 TECHNICAL MANUAL...
Page 540 (an interrupt can be generated). If only a part of an object/image is beyond the clipping area, the drawing within the clipping area is performed with- out an error. Seiko Epson Corporation 27-60 S1C33L26 TECHNICAL MANUAL...
Page 541 0). Therefore, a continuous mesh pattern will be generated even if two or more objects with mesh speci- fied overlap one another. Table 27. 6.8 Mesh Pattern Settings MESH_RW[1:0]/MESH_CW[1:0] Mesh size 4 pixels Reserved 2 pixels 1 pixel (Default: 0x0) Seiko Epson Corporation 27-61 S1C33L26 TECHNICAL MANUAL...
Page 542 0xfff R/W Cleared by writing _X[11:0] X coordinate any data. D[31:28] Reserved D[27:16] UPDT_UPL_Y[11:0]: Updated Area Upper Left Corner Y Coordinate Bits Indicates the Y coordinate value of the updated area upper left corner. (Default: 0xfff) Seiko Epson Corporation 27-62 S1C33L26 TECHNICAL MANUAL...
Page 543 (bcTable = 0). Conversion data must be written to the addresses shown above in advance. Addresses 0x302910 to 0x30291f is the 4 to 8 bpp conversion data area. Seiko Epson Corporation 27-63 S1C33L26 TECHNICAL MANUAL...
Page 544 ((VWIN_H + 1) × Y0 + X0) × bpp of main window upper ——————————————— ——————————————— left corner in work area (VWIN_W + 1) × bpp (VWIN_H + 1) × bpp Main screen address offset —————————— —————————— Seiko Epson Corporation 27-64 S1C33L26 TECHNICAL MANUAL...
Page 545 USB Function Controller (USB) 28.1 USB Function Controller Overview The S1C33L26 includes a USB function controller that supports Full-Speed mode defined in the USB2.0 Specifica- tion. The features are shown below. • Supports transfer at FS (12 Mbps). • Supports control, bulk, isochronous and interrupt transfers.
Page 546 Register name + register. Example: “MainInt register” * When a discrete bit is referred to: Register name. bit name + bit, or bit name + bit. Example: “MainIntStat.RcvEP0SETUP bit”, or “ForceNAK bit of the EP0ControlOUT register” Seiko Epson Corporation 28-2 S1C33L26 TECHNICAL MANUAL...
Page 547 The interface to the firmware is implemented through control and status registers as well as the interrupt signal which is asserted depending on the status. For settings that enable asserting interruption accord- ing to the status, see the section on register description. Seiko Epson Corporation 28-3 S1C33L26 TECHNICAL MANUAL...
Page 548 FIFO region. STALL response EPx{x=a,b,c,d}Control.ForceSTALL Returns a STALL response to the transaction. Transaction status EPx{x=a,b,c,d}IntStat.OUT_ShortACK, Indicates the result of the transaction. EPx{x=a,b,c,d}IntStat.IN_TranACK, EPx{x=a,b,c,d}IntStat.OUT_TranACK, EPx{x=a,b,c,d}IntStat.IN_TranNAK, EPx{x=a,b,c,d}IntStat.OUT_TranNAK, EPx{x=a,b,c,d}IntStat.IN_TranErr, EPx{x=a,b,c,d}IntStat.OUT_TranErr Seiko Epson Corporation 28-4 S1C33L26 TECHNICAL MANUAL...
Page 549 (b) Next, the host sends a data packet under the maximum packet size. The macro writes these data in the relevant endpoint’s FIFO. (c) Upon data reception, the macro automatically returns an ACK response. In addition, it sets registers to be automatically set up and issues a status to the firmware. Seiko Epson Corporation 28-5 S1C33L26 TECHNICAL MANUAL...
Page 550 (c) The host issues an IN transaction and executes a status stage, and the device returns a zero-length data packet. Control transfer without a data stage is executed as in this example but without the data stage. Seiko Epson Corporation 28-6 S1C33L26 TECHNICAL MANUAL...
Page 551 If it is an IN stage, set the INxOUT of the EP0Control register to set the direction to IN and control the stage by setting the EP0ControlIN accordingly. When the SETUP stage is completed, the ForceNAK bit is set. Seiko Epson Corporation 28-7 S1C33L26 TECHNICAL MANUAL...
Page 552 Also, you can refer to the DMA_Remain_H and DMA_Remain_L registers to check the number of remaining data. After the FIFO is emptied, the Port interface automatically pauses to perform flow control. Seiko Epson Corporation 28-8 S1C33L26 TECHNICAL MANUAL...
Page 553 Also, you can refer to the EPnWrRemain_H and EP- nWrRemain_L registers to check the available space in the FIFO. An attempt to write in a full FIFO causes dummy writing to be performed. Seiko Epson Corporation 28-9 S1C33L26 TECHNICAL MANUAL...
Page 554 (F7) As the FIFO now has some available space, Port transfer is resumed. (The PDREQ signal is asserted.) (F8) The macro responds to an IN transaction and transmits a data packet. Since the FIFO has some avail- able space, Port transfer continues. Seiko Epson Corporation 28-10 S1C33L26 TECHNICAL MANUAL...
Page 555 InSUSPEND == 0 CHK_EVENT LineState == SE0 LineState == K evt_DetectReset LineState == K WAIT_SE0 LineState == SE0 LineState == SE0 WAIT_SE0END RESUME state LineState == J DetectSeq = start Figure 28. 5.1.8 Auto-negotiator Seiko Epson Corporation 28-11 S1C33L26 TECHNICAL MANUAL...
Page 556 DisBusDetect bit to 1 and USBSNZ/MISC_USB register to 1 to start processing Snooze before reaching . As for self-powered products, however, the firmware does not have to perform Snooze. (Figure 28.5.1.9 shows the operation when Snooze is performed.) Seiko Epson Corporation 28-12 S1C33L26 TECHNICAL MANUAL...
Page 557 USB Suspend state cannot be pulled from the VBUS until 10 ms has elapsed after the Resume signal output. The S1C33L26 supports Snooze state. This section describes the operation for issuing Resume when the oscillation circuit is in operation (USBCLK_EN/CMU_CLKCTL register = 1, not in Sleep). Steps (3), (4), (8) and (9) below are handled by the macro hardware automatically.
Page 558 This section describes the operation that is carried out when the macro is connected to the hub or the host (via cable plug-in). Use the firmware that controls this macro to perform steps (3) and (4). Steps (1) and (2) are handled by the macro hardware automatically. Seiko Epson Corporation 28-14 S1C33L26 TECHNICAL MANUAL...
Page 559 Set ActiveUSB to 1. + 100 ms < T Set OpMode[1:0] to 0x0 (on the firmware). The downstream port sends out Reset. + 100 ms < T Set DisBusDetect to 1 (on the firmware). Seiko Epson Corporation 28-15 S1C33L26 TECHNICAL MANUAL...
Page 560 EPnControl.AllFIFO_Clr bit is cleared. This bit will never cause the RAM data to be cleared. Therefore, unless you have changed the descriptor area, there is no need to re-set the infor- mation recorded within the area since will never be cleared otherwise. Seiko Epson Corporation 28-16 S1C33L26 TECHNICAL MANUAL...
Page 561 CPU_JoinWr register. Note that, if the CPU_JoinRd register is set when register dumping is planned for debugging of a CPU using ICE, data will be read from the FIFO upon dumping the register. Seiko Epson Corporation 28-17 S1C33L26 TECHNICAL MANUAL...
Page 562 Basic operations This section describes the basic operations of the Port interface. Note that “DMA” in the descriptions refers to the DMA circuit in the USB macro and “DMAC” refers to the DMA controller module in the S1C33L26. Register setting Table 28.5.3.1 lists the registers used for setting basic items of the Port interface.
Page 563 (master) and then terminate the macro’s DMA transfer. Note: The S1C33L26 DMAC can only be triggered to start data transfer by the Rising Edge of PDREQ. After that no DMAC trigger will be issued while PDREQ stays active (high level) in multi-word DMA transfer mode.
Page 564 (master) and then terminate the macro’s DMA transfer. Note: The S1C33L26 DMAC can only be triggered to start data transfer by the Rising Edge of PDREQ. After that no DMAC trigger will be issued while PDREQ stays active (high level) in multi-word DMA transfer mode.
Page 565 (master) and then terminate the macro’s DMA transfer. Note: The S1C33L26 DMAC can only be triggered to start data transfer by the Rising Edge of PDREQ. The subsequent DMAC trigger will be issued at the next PDREQ Rising Edge. When the DMAC transfer counter reaches 0, DMA transfer will not be started even if a DMAC trigger is issued.
Page 566 (master) and then terminate the macro’s DMA transfer. Note: The S1C33L26 DMAC can only be triggered to start data transfer by the Rising Edge of PDREQ. The subsequent DMAC trigger will be issued at the next PDREQ Rising Edge. When the DMAC transfer counter reaches 0, DMA transfer will not be started even if a DMAC trigger is issued.
Page 567 OUT_TranACK IN_TranNAK OUT_TranNAK IN_TranErr OUT_TranErr 0x300c0a EPcIntStat R/(W) 0x00 – OUT_ShortACK IN_TranACK OUT_TranACK IN_TranNAK OUT_TranNAK IN_TranErr OUT_TranErr 0x300c0b EPdIntStat R/(W) 0x00 – OUT_ShortACK IN_TranACK OUT_TranACK IN_TranNAK OUT_TranNAK IN_TranErr OUT_TranErr 0x300c0c 0x300c0d 0x300c0e 0x300c0f Seiko Epson Corporation 28-23 S1C33L26 TECHNICAL MANUAL...
Page 568 0x300c42 EPcControl 0x00 AutoForceNAK EnShortPkt DisAF_NAK_Short ToggleStat ToggleSet ToggleClr ForceNAK ForceSTALL 0x300c43 EPdControl 0x00 AutoForceNAK EnShortPkt DisAF_NAK_Short ToggleStat ToggleSet ToggleClr ForceNAK ForceSTALL 0x300c44 0x300c45 0x300c46 0x300c47 0x300c48 0x300c49 0x300c4a 0x300c4b 0x300c4c 0x300c4d 0x300c4e 0x300c4f Seiko Epson Corporation 28-24 S1C33L26 TECHNICAL MANUAL...
Page 569 – – DMA_Latency[3:0] 0x300c98 DMA_Remain_H 0x00 – – – – DMA_Remain[11:8] 0x300c99 DMA_Remain_L 0x00 DMA_Remain[7:0] 0x300c9a 0x300c9b 0x300c9c DMA_Count_HH 0x00 DMA_Count[31:24] 0x300c9d DMA_Count_HL 0x00 DMA_Count[23:16] 0x300c9e DMA_Count_LH 0x00 DMA_Count[15:8] 0x300c9f DMA_Count_LL 0x00 DMA_Count[7:0] Seiko Epson Corporation 28-25 S1C33L26 TECHNICAL MANUAL...
Page 570 Set to 1 when the received data are set to the EP0Setup_0 to EP0Setup_7 after the set up stage has been completed. At the same time, the ForceSTALL bit, the ForceNAK bit and the ToggleStat bit of the EP- 0ControlIN and EP0ControlOUT registers are automatically set to 0, 1 and 1, respectively. Seiko Epson Corporation 28-26 S1C33L26 TECHNICAL MANUAL...
Page 571 When the AutoSetAddress function (refer to the USB_Address register) ends normally, this bit is set to 1. The case when AutoSetAddress function ends normally is that when ACK is received during IN trans- action. Seiko Epson Corporation 28-27 S1C33L26 TECHNICAL MANUAL...
Page 572 – – – 0 when being read. status) FIFO_IN_Cmp 1 IN FIFO Complete 0 None R(W) FIFO_OUT_Cmp 1 OUT FIFO complete 0 None R(W) This register displays the interrupt status of the FIFO. Seiko Epson Corporation 28-28 S1C33L26 TECHNICAL MANUAL...
Page 573 Set to 1 when STALL is replied in the IN transaction, when an error occurred in the packet or when the handshake is failed in Time-Out. OUT_TranErr Shows a cause of interrupt directly. Set to 1 when STALL is replied in the OUT transaction or when an error occurred in the packet. Seiko Epson Corporation 28-29 S1C33L26 TECHNICAL MANUAL...
Page 574 Shows a cause of interrupt directly. Set to 1 when a short packet is received and ACK is replied in the OUT transaction, OUT_TranACK and this bits are set to 1 at the same time. Seiko Epson Corporation 28-30 S1C33L26 TECHNICAL MANUAL...
Page 575 Set to 1 when NAK is replied in the IN transaction. OUT_TranNAK Shows a cause of interrupt directly. Set to 1 when NAK is replied in the OUT transaction. IN_TranErr Shows a cause of interrupt directly. Seiko Epson Corporation 28-31 S1C33L26 TECHNICAL MANUAL...
Page 576 This register enables/disables assertion of the interrupt signal (#INT) with the cause of interrupt of the MainIntStat register. Setting the corresponding bit to 1 enables interrupt. EnSIE_IntStat bit is valid during snooze as well. Seiko Epson Corporation 28-32 S1C33L26 TECHNICAL MANUAL...
Page 577 (8 bits) 1 Enable 0 Disable enable) EnOUT_TranACK EnIN_TranNAK EnOUT_TranNAK EnIN_TranErr EnOUT_TranErr This register enables/disables assertion of the EP0IntStat bit of the MainIntStat register with the cause of interrupt of the EP0IntStat register. Seiko Epson Corporation 28-33 S1C33L26 TECHNICAL MANUAL...
Page 578 Init. R/W Remarks RevisionNum 0x300c20 D7–0 RevisionNum[7:0] Revision number 0x12 (Revision (8 bits) (0x12) number) This register shows the revision number of the USB function controller. This register is valid during snooze as well. Seiko Epson Corporation 28-34 S1C33L26 TECHNICAL MANUAL...
Page 579 1 FS mode (fixed) 0 – D5–2 – – – – 0 when being read. D1–0 LineState[1:0] LineState[1:0] DP/DM This register displays the status related to the USB. This register is valid during snooze as well. Seiko Epson Corporation 28-35 S1C33L26 TECHNICAL MANUAL...
Page 580 The operation setting is done in this register for the USB test mode. Set the bit corresponding to the test mode specified by the SetFeature request, and after completing the status stage, set the EnUSB_Test bit to 1 and perform the test mode operation defined by the USB standard. Seiko Epson Corporation 28-36 S1C33L26 TECHNICAL MANUAL...
Page 581 D4–1 – – – – EP0FIFO_Clr 1 Clear EP0 FIFO 0 Do nothing This register sets operations of entire endpoints, and display them. AllForceNAK Sets the ForceNAK bit of all endpoints to 1. Seiko Epson Corporation 28-37 S1C33L26 TECHNICAL MANUAL...
Page 582 DMA_Join register is set to 1) and the start operation of the general port is being done (when the DMA_Running bit of the DMA_Control register is 1). Otherwise, a malfunction may occur. Seiko Epson Corporation 28-38 S1C33L26 TECHNICAL MANUAL...
Page 583 EP0Setup_5 register The upper order 8 bits in WIndex are set. EP0Setup_6 register The lower order 8 bits in WLength are set. EP0Setup_7 register The upper order 8 bits in WLength are set. Seiko Epson Corporation 28-39 S1C33L26 TECHNICAL MANUAL...
Page 584 DescAdrs_H, L register, and its data size is specified in the DescSize_H, L register. Since these setting values are updated during execution of the Descriptor reply function, set these set- ting values every time setting the ReplyDescriptor bit. Seiko Epson Corporation 28-40 S1C33L26 TECHNICAL MANUAL...
Page 585 0 (to be cleared), and this bit cannot be set to 1 as long as the RcvEP0SETUP bit is 1. When a transaction has been being done for a certain period of time, the setting of this bit will be en- abled from the next transaction. Seiko Epson Corporation 28-41 S1C33L26 TECHNICAL MANUAL...
Page 586 0 when being read. Reserved D[6:3] EP0MaxSize[6:3] This register sets the MaxPacketSize of the endpoint EP0. The size of this endpoint can be set to 8, 16, 32 or 64 bytes. D[2:0] Reserved Seiko Epson Corporation 28-42 S1C33L26 TECHNICAL MANUAL...
Page 587 ForceNAK bit. When a transaction has been being done for a certain period of time, the setting of this bit will be en- abled from the next transaction. Seiko Epson Corporation 28-43 S1C33L26 TECHNICAL MANUAL...
Page 588 1 Set toggle sequence bit 0 Do nothing W 0 when being read. ToggleClr 1 Clear toggle sequence bit 0 Do nothing ForceNAK 1 Force NAK 0 Do nothing ForceSTALL 1 Force STALL 0 Do nothing Seiko Epson Corporation 28-44 S1C33L26 TECHNICAL MANUAL...
Page 589 1 Force STALL 0 Do nothing This register sets operations of the endpoint EPd. AutoForceNAK Sets the ForceNAK bit of this register to 1 when the transaction of the endpoint EPd completes nor- mally. Seiko Epson Corporation 28-45 S1C33L26 TECHNICAL MANUAL...
Page 590 When using this endpoint for the interrupt transfer, up to 64 bytes can be set. If the area of the endpoint EPa is smaller than specified here, the macro does not operate normally. Seiko Epson Corporation 28-46 S1C33L26 TECHNICAL MANUAL...
Page 591 (EPb max (8 bits) D1–0 EPbMaxSize[9:8] Endpoint EPb max packet size 0x0 R/W packet size high) EPbMaxSize_L 0x300c55 D7–0 EPbMaxSize[7:0] Endpoint EPb max packet size 0x0 R/W (EPb max (8 bits) packet size low) Seiko Epson Corporation 28-47 S1C33L26 TECHNICAL MANUAL...
Page 592 According to USB spec, a packet must be discarded when CRC error occurs in isochronous transaction. When this bit is set, a packet with CRC error is not discarded. This bit is valid when ISO bit (D7) is set. D[5:0] Reserved Seiko Epson Corporation 28-48 S1C33L26 TECHNICAL MANUAL...
Page 593 0 when being read. This register sets up the endpoint EPc. Perform the setup so that combination of the EndpointNumber and the INxOUT does not overlap with those of other endpoints. Sets the isochronous mode. Seiko Epson Corporation 28-49 S1C33L26 TECHNICAL MANUAL...
Page 594 0x300c5f 1 ISO 0 Non-ISO (EPd (8 bits) ISO_CRCmode 1 CRC mode 0 Normal ISO configuration 1) D5–0 – – – – 0 when being read. This register sets up the endpoint EPd. Seiko Epson Corporation 28-50 S1C33L26 TECHNICAL MANUAL...
Page 595 After setting the StartAdrs of all endpoints, be sure to set the AllFIFO_Clr bit of the EPnControl regis- ter to 1 to clear all FIFOs. If the EPbMaxSize of the endpoint EPb is larger than the area specified in here, the macro does not op- erate normally. Seiko Epson Corporation 28-51 S1C33L26 TECHNICAL MANUAL...
Page 596 After setting the StartAdrs of all endpoints, be sure to set the AllFIFO_Clr bit of the EPnControl regis- ter to 1 to clear all FIFOs. If the EPdMaxSize of the endpoint EPd is larger than the area specified in here, the macro does not op- erate normally. Seiko Epson Corporation 28-52 S1C33L26 TECHNICAL MANUAL...
Page 597 1 Join EPd FIFO write 0 Do nothing write) JoinEPcWr 1 Join EPc FIFO write 0 Do nothing JoinEPbWr 1 Join EPb FIFO write 0 Do nothing JoinEPaWr 1 Join EPa FIFO write 0 Do nothing Seiko Epson Corporation 28-53 S1C33L26 TECHNICAL MANUAL...
Page 598 EPnFIFOforCPU 0x300c83 D7–0 EPnFIFOData[7:0] Endpoint n FIFO access from CPU (EPn FIFO for (8 bits) CPU) D[7:0] EPnFIFOData[7:0] This register is used for accessing the FIFO of the endpoint from the CPU Interface. Seiko Epson Corporation 28-54 S1C33L26 TECHNICAL MANUAL...
Page 599 D7–4 – – – – 0 when being read. (Descriptor (8 bits) D3–0 DescAdrs[11:8] Descriptor address 0x0 R/W address high) DescAdrs_L 0x300c89 D7–0 DescAdrs[7:0] Descriptor address 0x0 R/W (Descriptor (8 bits) address low) Seiko Epson Corporation 28-55 S1C33L26 TECHNICAL MANUAL...
Page 600 Thus the Descriptor reply function protects these data from deletion and overwriting. However, if the area where the Descriptor data is written into, is overlapped with the area secured by other endpoints, the data will be overwritten. Seiko Epson Corporation 28-56 S1C33L26 TECHNICAL MANUAL...
Page 601 This register controls the DMA transfer and shows the status of the interface. DMA_Running This bit is automatically set 1 during the DMA transfer. The DMA_Join register cannot be written when this bit is 1. Seiko Epson Corporation 28-57 S1C33L26 TECHNICAL MANUAL...
Page 602 1 Single word 0 Multi word D2–1 – – – – 0 when being read. CountMode 1 Count-down mode 0 Free-run mode This register sets fields on the operation mode of the DMA interface. Seiko Epson Corporation 28-58 S1C33L26 TECHNICAL MANUAL...
Page 603 MaxSize register + 32-byte or larger area, into the EP{a,b,c,d}StartAdrs register. Note: In the S1C33L26, the USB DMA data transfer count is determined according to the DMAC transfer counter setting. Negating PDREQ by the USB macro does not affect the transfer count.
Page 604 DMA_Count[31:0] These registers specify the data length in the DMA transfer in units of byte, and displays it. Its setting can be done as large as up to 0xffffffff bytes. Seiko Epson Corporation 28-60 S1C33L26 TECHNICAL MANUAL...
Page 605 DMA. When it reaches 0x00000000, the DMA ends. In this mode, the remained quantity of the data to transfer can be referred. Writing into these registers during the DMA transfer is neglected. For reading these registers, access the DMA_Count_HH, HL, LH and LL registers in this order. Seiko Epson Corporation 28-61 S1C33L26 TECHNICAL MANUAL...
Page 606 0 cycles Cannot be set (Default: 0x7) Note: The S1C33L26 RTC cannot operate if RTCWT[2:0] is set to 0x0 (0 wait cycles). 29.2 Internal RAM Wait Control The MISC_RAMWT register contains COREWT and BUSWT to set the number of wait cycles (in MCLK) to be inserted when accessing IRAM (Area 0) and IVRAM (Area 3), respectively.
Page 607 Note: When programming a Flash memory on the target board, BOOT_ENA must be set to 0. Be sure to avoid changing the boot mode when writing data to the MISC_BOOT register. For more information on booting, see “Boot” in Appendix. Seiko Epson Corporation 29-2 S1C33L26 TECHNICAL MANUAL...
Page 608 Cannot be set (Default: 0x7) The number of wait cycles should be set according to the MCLK clock frequency. Note: The S1C33L26 RTC cannot operate if RTCWT[2:0] is set to 0x0 (0 wait cycles). USB Configuration Register (MISC_USB) Register name Address...
Page 609 If IVRAM is relocated to Area 0, the COREWT setting is ineffective. Table 29. 6.5 BUSWT (IVRAM Wait Cycle) Settings BUSWT Number of wait cycles MCLK frequency 1 cycle ≤ 60 MHz MCLK 0 cycles Seiko Epson Corporation 29-4 S1C33L26 TECHNICAL MANUAL...
Page 610 Note: When DSTRAM is switched to LUTRAM, locate the DMAC control table in IVRAM (Area 3) or an external RAM. D[3:1] Reserved IVRAM_LOC: IVRAM Location Select Bit Selects the 20KB IVRAM location. 1 (R/W): Area 3 (default) 0 (R/W): Area 0 Seiko Epson Corporation 29-5 S1C33L26 TECHNICAL MANUAL...
Page 611 0x96. When rewriting the Misc reg- isters has finished, PROT[7:0] should be set to other than 0x96 to prevent accidental writing to the Misc registers. Seiko Epson Corporation 29-6 S1C33L26 TECHNICAL MANUAL...
Page 612 30 DIVIDER (DIV) Divider (DIV) The S1C33L26 has an embedded coprocessor that provides a signed/unsigned 16 ÷ 16-bit division function. This section explains how to use the divider. Argument 2 (divisor) Argument 1 (dividend) 16 bits ÷ Mode setting Divider...
Page 613 Input fall time (Schmitt input) – – – *1) HV ≥ LV /RTCV /PLLV = RTCV = PLLV *2) The recommended input voltage range of the #STBY pin is V - 0.3 V to 3.6 V. Seiko Epson Corporation 31-1 S1C33L26 TECHNICAL MANUAL...
Page 614 High level input voltage (LVCMOS) = 3.6V – + 0.3 IH2H Low level input voltage (LVCMOS) = 2.7V – – IL2H Positive trigger input voltage (LVCMOS Schmitt) V = 3.6V, LV = 1.95V – Seiko Epson Corporation 31-2 S1C33L26 TECHNICAL MANUAL...
Page 615 – – *1, *3 CPU clock = 48MHz – – Current consumption during execution CPU clock = 60MHz – – (CPU/CCU/IRAM) OSC3 = 48MHz, SYSCLK = PLL out (60MHz), CPU clock = SYSCLK Seiko Epson Corporation 31-3 S1C33L26 TECHNICAL MANUAL...
Page 616 • The GPIO ports are all configured to input with pulled up (no floating input). • The current consumption is measured by executing a test program that consists of 51% load instructions, 21% arithmetic opera- tion instructions, 10% branch instructions and 18% ext instructions. Seiko Epson Corporation 31-4 S1C33L26 TECHNICAL MANUAL...
Page 617 Zero scale error E [LSB] 1LSB V'[001]h Analog input Full scale error V[3FF]h (=1022.5LSB) V'[3FF]h (V'[3FF]h + 0.5LSB') - (V[3FF]h + 0.5LSB) Full scale error E [LSB] 1LSB Actual conversion characteristic Ideal conversion characteristic Analog input Seiko Epson Corporation 31-5 S1C33L26 TECHNICAL MANUAL...
Page 618 = 0V, Ta = 25°C Item Symbol Condition Min. Typ. Max. Unit Oscillation start time – – STA3 *1) When the recommended parts shown in the “Basic External Wiring Diagram” chapter are used Seiko Epson Corporation 31-6 S1C33L26 TECHNICAL MANUAL...
Page 619 C3ED OSC3 external clock input rise time – – OSC3 external clock input fall time – – 31.8.2 SRAMC AC Characteristics SRAM read cycle MCLK CMU_CLK valid A[25:0] #CEx RDDH valid D[15:0] #WAIT Seiko Epson Corporation 31-7 S1C33L26 TECHNICAL MANUAL...
Page 620 #SDCS RASD RASH #SDRAS CASD CASH #SDCAS #SDWE (read) (write) D[15:0] valid valid valid DQMD DQMH DQMH/ DQML * Read: CAS latency = 2, burst length = 2 Write: single write Seiko Epson Corporation 31-8 S1C33L26 TECHNICAL MANUAL...
Page 621 SDRAM auto-refresh cycle Auto refresh SDCLK SDCKE SDBA[1:0] SDA[12:11] SDA[9:0] SDA10 #SDCS RASD RASH #SDRAS CASD CASH #SDCAS #SDWE D[15:0] DQMH/ DQML * A precharge cycle is necessary before entering the auto refresh mode. Seiko Epson Corporation 31-9 S1C33L26 TECHNICAL MANUAL...
Page 622 – 12.1 #SDWE signal hold time – – Read data setup time – – Read data hold time – – Write data delay time – – 12.1 Write data hold time – – Seiko Epson Corporation 31-10 S1C33L26 TECHNICAL MANUAL...
Page 623 Typ. Max. Unit spi_ck cycle time 85 + t – – SPCK PCLK spi_di setup time 85 + t – – PCLK spi_di hold time – – spi_do output delay time – – Seiko Epson Corporation 31-11 S1C33L26 TECHNICAL MANUAL...
Page 624 = 2.7 to 3.6V, V = 0V, Ta = -40 to 85°C Item Symbol Min. Typ. Max. Unit spi_ck cycle time 85 + t – – SPCK PCLK spi_do output delay time – – Seiko Epson Corporation 31-12 S1C33L26 TECHNICAL MANUAL...
Page 625 HDP (Horizontal Display Period) HNDP (Horizontal Non-Display Period) = (HTCNT[6:0] - HDPCNT[6:0]) × 8 (Ts) VDP (Vertical Display Period) = VDPCNT[9:0] + 1 (lines) VNDP (Vertical Non-Display Period) = VTCNT[9:0] - VDPCNT[9:0] (lines) Seiko Epson Corporation 31-13 S1C33L26 TECHNICAL MANUAL...
Page 626 = pixel clock period 2. t - 9 (Ts) 1min 3min 3. t = HDP + HNDP (Ts) 3min 4. t = HNDP + 2 (Ts) 6min 5. t = HNDP + 11 (Ts) 7min Seiko Epson Corporation 31-14 S1C33L26 TECHNICAL MANUAL...
Page 627 HDP (Horizontal Display Period) HNDP (Horizontal Non-Display Period) = (HTCNT[6:0] - HDPCNT[6:0]) × 8 (Ts) VDP (Vertical Display Period) = VDPCNT[9:0] + 1 (lines) VNDP (Vertical Non-Display Period) = VTCNT[9:0] - VDPCNT[9:0] (lines) Seiko Epson Corporation 31-15 S1C33L26 TECHNICAL MANUAL...
Page 628 = pixel clock period 2. t - 9 (Ts) 1min 3min 3. t = HDP + HNDP (Ts) 3min 4. t = HNDP + 4 (Ts) 6min 5. t = HNDP + 13 (Ts) 7min Seiko Epson Corporation 31-16 S1C33L26 TECHNICAL MANUAL...
Page 629 HDP (Horizontal Display Period) HNDP (Horizontal Non-Display Period) = (HTCNT[6:0] - HDPCNT[6:0]) × 8 (Ts) VDP (Vertical Display Period) = VDPCNT[9:0] + 1 (lines) VNDP (Vertical Non-Display Period) = VTCNT[9:0] - VDPCNT[9:0] (lines) Seiko Epson Corporation 31-17 S1C33L26 TECHNICAL MANUAL...
Page 630 = pixel clock period 2. t - 9 (Ts) 1min 3min 3. t = HDP + HNDP (Ts) 3min 4. t = HNDP + 1.5 (Ts) 6min 5. t = HNDP + 10.5 (Ts) 7min Seiko Epson Corporation 31-18 S1C33L26 TECHNICAL MANUAL...
Page 631 HDP (Horizontal Display Period) HNDP (Horizontal Non-Display Period) = (HTCNT[6:0] - HDPCNT[6:0]) × 8 (Ts) VDP (Vertical Display Period) = VDPCNT[9:0] + 1 (lines) VNDP (Vertical Non-Display Period) = VTCNT[9:0] - VDPCNT[9:0] (lines) Seiko Epson Corporation 31-19 S1C33L26 TECHNICAL MANUAL...
Page 632 = HNDP + t + 1 (Ts) 6amin 5. t = HNDP + t + 1 (Ts) 6bmin 6. t = HNDP + 11 (Ts) 7amin 7. t = HNDP + 11 - t (Ts) 7bmin Seiko Epson Corporation 31-20 S1C33L26 TECHNICAL MANUAL...
Page 633 HDP (Horizontal Display Period) HNDP (Horizontal Non-Display Period) = (HTCNT[6:0] - HDPCNT[6:0]) × 8 (Ts) VDP (Vertical Display Period) = VDPCNT[9:0] + 1 (lines) VNDP (Vertical Non-Display Period) = VTCNT[9:0] - VDPCNT[9:0] (lines) Seiko Epson Corporation 31-21 S1C33L26 TECHNICAL MANUAL...
Page 634 = pixel clock period 2. t - 9 (Ts) 1min 3min 3. t = HDP + HNDP (Ts) 3min 4. t = HNDP + 1 (Ts) 6min 5. t = HNDP + 10 (Ts) 7min Seiko Epson Corporation 31-22 S1C33L26 TECHNICAL MANUAL...
Page 635 3 – Lines Vertical sync pulse width – – Lines note) 1. t = VTCNT[9:0] + 1 (Lines) 1typ 2. t = VDPSCNT[9:0] (Lines) 2typ 3. t = VDPCNT[9:0] + 1 (Lines) 3typ Seiko Epson Corporation 31-23 S1C33L26 TECHNICAL MANUAL...
Page 636 – Output signal crossover voltage *4 – *3) Refer to Section 7.1.1 in the USB2.0 Specification for the conditions. *4) Refer to Figures 7-8 and 7-9 in the USB2.0 Specification for the conditions. Seiko Epson Corporation 31-24 S1C33L26 TECHNICAL MANUAL...
Page 637 VBUS input impedance R1 + R2 – – VBUS VBUS resistor ratio R1 : R2 1 : 2 (nominal) – *6) Refer to Figures 7-8 and 7-9 in the USB2.0 Specification for the conditions. Seiko Epson Corporation 31-25 S1C33L26 TECHNICAL MANUAL...
Page 638 PWM_L T16A_EXCL_x 16-bit PWM timer T16A_ATMA_x (T16A5) input/output T16A_ATMB_x REMC_I Remote transmitter/ receiver REMC_O * The #STBY pin should be fixed at the RTCV level if it is not used for power control. Seiko Epson Corporation 32-1 S1C33L26 TECHNICAL MANUAL...
Page 639 Notes: • The values in the above table are shown only for reference and not guaranteed. • Crystal and ceramic resonators are extremely sensitive to influence of external components and printed-circuit boards. Before using a resonator, please contact the manufacturer for fur- ther information on conditions of use. Seiko Epson Corporation 32-2 S1C33L26 TECHNICAL MANUAL...
Page 640 Control P6 port input/output direction 0x30030e GPIO_P7_DAT P7 Port Data Register P7 port input data 0x300310 GPIO_P8_DAT P8 Port Data Register P8 port input/output data 0x300311 GPIO_P8_IOC P8 Port I/O Control Register Control P8 port input/output direction Seiko Epson Corporation AP-A-1 S1C33L26 TECHNICAL MANUAL...
Page 641 0x30080a PMUX_P5_03 P5[3:0] Port Function Select Register Select P5[3:0] port functions 0x30080b PMUX_P5_46 P5[6:4] Port Function Select Register Select P5[6:4] port functions 0x30080c PMUX_P6_0 P60 Port Function Select Register Select P60 port functions Seiko Epson Corporation AP-A-2 S1C33L26 TECHNICAL MANUAL...
Page 642 0x300703 FSIO_CTL0 FSIO Ch.0 Control Register Set transfer mode and control data transfer 0x300704 FSIO_IRDA0 FSIO Ch.0 IrDA Register Set IrDA conditions 0x300705 FSIO_BRTRUN0 FSIO Ch.0 Baud-rate Timer Control Register Control baud-rate timer Seiko Epson Corporation AP-A-3 S1C33L26 TECHNICAL MANUAL...
Page 643 0x300c21 USB_Control USB Control Register Control USB conditions 0x300c22 USB_Status USB Status Register Indicate USB status 0x300c23 XcvrControl Xcvr Control Register Control transceiver macro 0x300c24 USB_Test USB Test Register Set USB test mode Seiko Epson Corporation AP-A-4 S1C33L26 TECHNICAL MANUAL...
Page 644 DMA Latency Register Set data transfer latency 0x300c98 DMA_Remain_H DMA FIFO Remain High Register Indicate remained data quantity in FIFO or free space capacity in FIFO 0x300c99 DMA_Remain_L DMA FIFO Remain Low Register Seiko Epson Corporation AP-A-5 S1C33L26 TECHNICAL MANUAL...
Page 645 T16A5 Ch.1 Counter Data Register Counter data Ch.1 0x301194 T16A_CCCTL1 T16A5 Ch.1 Comparator/Capture Control Register Control comparator/capture block and TOUT (16-bit device) 0x301196 T16A_CCA1 T16A5 Ch.1 Comparator/Capture A Data Register Compare A/capture A data Seiko Epson Corporation AP-A-6 S1C33L26 TECHNICAL MANUAL...
Page 646 Control software trigger and indicate trigger status 0x302114 DMAC_END_FLG DMAC End-of-Transfer Flag Register Indicate DMA completed channels 0x302118 DMAC_RUN_ DMAC Running Status Register Indicates running channel STAT 0x30211c DMAC_PAUSE_ DMAC Pause Status Register Indicate DMA suspended channels STAT Seiko Epson Corporation AP-A-7 S1C33L26 TECHNICAL MANUAL...
Page 647 • When data is written to the registers, the “Reserved” bits must always be written as 0 and not 1, except RTCIMD/RTC_INTMODE register (D1/0x300a01) for RTC. • When accessing the USB registers, the USBCLK clock must be supplied to the USB function controller in addition to USBREGCLK. Seiko Epson Corporation AP-A-8 S1C33L26 TECHNICAL MANUAL...
Page 648 524,288 cycles 1,048,576 cycles 2,097,152 cycles 4,194,304 cycles D3–2 – reserved – – – 0 when being read. OSC1EN OSC1 enable 1 Enable 0 Disable R/W Write-protected OSC3EN OSC3 enable 1 Enable 0 Disable Seiko Epson Corporation AP-A-9 S1C33L26 TECHNICAL MANUAL...
Page 649 0 when being read. Division Ratio (8 bits) D3–0 PLLINDIV PLL input clock division ratio PLLINDIV[3:0] Division ratio 0x7 R/W Clock source = Select Register [3:0] select 0xf–0xa OSC3 (CMU_ 1/10 Write-protected PLLINDIV) Seiko Epson Corporation AP-A-10 S1C33L26 TECHNICAL MANUAL...
Page 650 1 to 7 0x0 R/W (ITC_FPT47_LV) FPT8–B 0x300212 D7–3 – reserved – – – 0 when being read. Interrupt Level (8 bits) D2–0 INT_LV[2:0] FPT8–B interrupt level Register 1 to 7 0x0 R/W (ITC_FPT8B_LV) Seiko Epson Corporation AP-A-11 S1C33L26 TECHNICAL MANUAL...
Page 651 1 to 7 0x0 R/W REMC Interrupt 0x300228 D7–3 – reserved – – – 0 when being read. Level Register (8 bits) D2–0 INT_LV[2:0] REMC interrupt level 1 to 7 0x0 R/W (ITC_REMC_LV) Seiko Epson Corporation AP-A-12 S1C33L26 TECHNICAL MANUAL...
Page 652 – – – 0 when being read. Register (8 bits) D3–0 P8[3:0]D P8[3:0] I/O port data 1 1 (High) 0 0 (Low) Ext. R/W Ext.: Depends on (GPIO_P8_DAT) the external pin status. Seiko Epson Corporation AP-A-13 S1C33L26 TECHNICAL MANUAL...
Page 653 – – – 0 when being read. Control Register (8 bits) D6–0 PUPA[6:0] R/W * PA1: pulled up, PA[6:0] port pull-up enable 1 Enable 0 Disable (GPIO_PA_PUP) others: not pulled up Write-protected Seiko Epson Corporation AP-A-14 S1C33L26 TECHNICAL MANUAL...
Page 654 D5–4 SPTA[1:0] FPTA interrupt input port select SPTA[1:0] Port 0x0 R/W D3–2 SPT9[1:0] FPT9 interrupt input port select SPT9[1:0] Port 0x0 R/W D1–0 SPT8[1:0] FPT8 interrupt input port select SPT8[1:0] Port 0x0 R/W Seiko Epson Corporation AP-A-15 S1C33L26 TECHNICAL MANUAL...
Page 655 FPT7 interrupt enable 1 Enable 0 Disable Register SIET6 FPT6 interrupt enable 1 Enable 0 Disable (GPIO_FPT47_ SIET5 FPT5 interrupt enable 1 Enable 0 Disable MSK) SIET4 FPT4 interrupt enable 1 Enable 0 Disable Seiko Epson Corporation AP-A-16 S1C33L26 TECHNICAL MANUAL...
Page 656 – reserved – – – 0 when being read. D2–0 SCTP2[2:0] FPT2 chattering filter time select Filter sampling 0x0 R/W SCTP2[2:0] time 64/f PCLK2 32/f PCLK2 16/f PCLK2 PCLK2 PCLK2 PCLK2 PCLK2 None Seiko Epson Corporation AP-A-17 S1C33L26 TECHNICAL MANUAL...
Page 657 – reserved – – – 0 when being read. D2–0 SCTP8[2:0] FPT8 chattering filter time select Filter sampling 0x0 R/W SCTP8[2:0] time 64/f PCLK2 32/f PCLK2 16/f PCLK2 PCLK2 PCLK2 PCLK2 PCLK2 None Seiko Epson Corporation AP-A-18 S1C33L26 TECHNICAL MANUAL...
Page 658 – reserved – – – 0 when being read. D2–0 SCTPE[2:0] FPTE chattering filter time select Filter sampling 0x0 R/W SCTPE[2:0] time 64/f PCLK2 32/f PCLK2 16/f PCLK2 PCLK2 PCLK2 PCLK2 PCLK2 None Seiko Epson Corporation AP-A-19 S1C33L26 TECHNICAL MANUAL...
Page 659 CFP12[1:0] Function 0x0 R/W T16A_ATMA_1 FPDAT10 USIL_CS D3–2 CFP11[1:0] P11 port function select CFP11[1:0] Function 0x0 R/W reserved FPDAT9 USIL_DO D1–0 CFP10[1:0] P10 port function select CFP10[1:0] Function 0x0 R/W reserved FPDAT8 USIL_DI Seiko Epson Corporation AP-A-20 S1C33L26 TECHNICAL MANUAL...
Page 660 0x0 R/W Write-protected Register reserved (PMUX_P3_46) reserved DST2 D3–2 CFP35[1:0] P35 port function select CFP35[1:0] Function 0x0 R/W reserved reserved DSIO D1–0 CFP34[1:0] P34 port function select CFP34[1:0] Function 0x0 R/W reserved reserved DCLK Seiko Epson Corporation AP-A-21 S1C33L26 TECHNICAL MANUAL...
Page 661 CFP72[1:0] Function 0x0 R/W reserved PWM_EXCL AIN2 D3–2 CFP71[1:0] P71 port function select CFP71[1:0] Function 0x0 R/W reserved T16A_EXCL_1 AIN1 D1–0 CFP70[1:0] P70 port function select CFP70[1:0] Function 0x0 R/W reserved T16A_EXCL_0 AIN0 Seiko Epson Corporation AP-A-22 S1C33L26 TECHNICAL MANUAL...
Page 662 CFP96[1:0] Function 0x0 R/W reserved LCD_D6 FPDAT6 D3–2 CFP95[1:0] P95 port function select CFP95[1:0] Function 0x0 R/W reserved LCD_D5 FPDAT5 D1–0 CFP94[1:0] P94 port function select CFP94[1:0] Function 0x0 R/W reserved LCD_D4 FPDAT4 Seiko Epson Corporation AP-A-23 S1C33L26 TECHNICAL MANUAL...
Page 663 CFPB6[1:0] Function 0x0 R/W FPDAT22 reserved FPDAT14 D3–2 CFPB5[1:0] PB5 port function select CFPB5[1:0] Function 0x0 R/W FPDAT21 reserved FPDAT13 D1–0 CFPB4[1:0] PB4 port function select CFPB4[1:0] Function 0x0 R/W FPDAT20 reserved FPDAT12 Seiko Epson Corporation AP-A-24 S1C33L26 TECHNICAL MANUAL...
Page 664 TD7 = MSB Buffer Register TD0 = LSB (USI_TD) USI Receive 0x300402 D7–0 RD[7:0] USI receive data buffer 0x0 to 0xff Data Buffer (8 bits) RD7 = MSB Register RD0 = LSB (USI_RD) Seiko Epson Corporation AP-A-25 S1C33L26 TECHNICAL MANUAL...
Page 665 End of Rx data End of Tx data Stop generated Start generated IMEIF Overrun error flag 1 Error 0 Normal R/W Reset by writing 1. IMIF Operation completion flag 1 Completed 0 Not completed Seiko Epson Corporation AP-A-26 S1C33L26 TECHNICAL MANUAL...
Page 666 Framing error flag 1 Error 0 Normal UOEIF Overrun error flag 1 Error 0 Normal URDIF Receive buffer full flag 1 Full 0 Not full UTDIF Transmit buffer empty flag 1 Empty 0 Not empty Seiko Epson Corporation AP-A-27 S1C33L26 TECHNICAL MANUAL...
Page 667 – – – 0 when being read. Mode Interrupt (8 bits) Enable Register (USIL_ISIE) ISEIE Receive error interrupt enable 1 Enable 0 Disable ISIE Operation completion int. enable 1 Enable 0 Disable Seiko Epson Corporation AP-A-28 S1C33L26 TECHNICAL MANUAL...
Page 668 D5–4 LPST[1:0] Setup cycle LPST[1:0] Setup cycle 0x0 R/W 4 cycles 3 cycles 2 cycles 1 cycle D3–0 LPWT[3:0] Wait cycle LPWT[3:0] Wait cycle 0x0 R/W 15 cycles 14 cycles 1 cycle 0 cycles Seiko Epson Corporation AP-A-29 S1C33L26 TECHNICAL MANUAL...
Page 669 – – – 0 when being read. Baud-rate Timer (8 bits) Count Data H D3–0 BRTCD Register Baud-rate timer count data [11:8] 0x0 to 0xf (FSIO_ [11:8] (BRTCD[11:0] = 0x0 to 0xfff) BRTCDH0) Seiko Epson Corporation AP-A-30 S1C33L26 TECHNICAL MANUAL...
Page 670 1 Run 0 Stop FSIO Ch.1 0x300716 D7–0 BRTRD[7:0] Baud-rate timer reload data [7:0] 0x0 to 0xff 0x0 R/W Baud-rate Timer (8 bits) (BRTRD[11:0] = 0x0 to 0xfff) Reload Data L Register (FSIO_ BRTRDL1) Seiko Epson Corporation AP-A-31 S1C33L26 TECHNICAL MANUAL...
Page 671 – – – 0 when being read. Register (8 bits) D5–4 RTCDH[1:0] RTC 10-day counter 0 to 3 X (*) R/W (RTC_DAY) D3–0 RTCDL[3:0] RTC 1-day counter 0 to 9 X (*) R/W Seiko Epson Corporation AP-A-32 S1C33L26 TECHNICAL MANUAL...
Page 672 R(W) IN_TranNAK 1 In transaction NAK 0 None R(W) OUT_TranNAK 1 Out transaction NAK 0 None R(W) IN_TranErr 1 In transaction error 0 None R(W) OUT_TranErr 1 Out transaction error 0 None R(W) Seiko Epson Corporation AP-A-33 S1C33L26 TECHNICAL MANUAL...
Page 673 EnFIFO_IN_Cmp 1 Enable 0 Disable EnFIFO_OUT_Cmp EP0IntEnb 0x300c17 D7–6 – – – – 0 when being read. EnIN_TranACK (EP0 interrupt (8 bits) 1 Enable 0 Disable enable) EnOUT_TranACK EnIN_TranNAK EnOUT_TranNAK EnIN_TranErr EnOUT_TranErr Seiko Epson Corporation AP-A-34 S1C33L26 TECHNICAL MANUAL...
Page 674 EPdFIFO_Clr 1 Clear EPd FIFO 0 Do nothing clear) EPcFIFO_Clr 1 Clear EPc FIFO 0 Do nothing EPbFIFO_Clr 1 Clear EPb FIFO 0 Do nothing EPaFIFO_Clr 1 Clear EPa FIFO 0 Do nothing Seiko Epson Corporation AP-A-35 S1C33L26 TECHNICAL MANUAL...
Page 675 1 Set toggle sequence bit 0 Do nothing W 0 when being read. ToggleClr 1 Clear toggle sequence bit 0 Do nothing ForceNAK 1 Force NAK 0 Do nothing ForceSTALL 1 Force STALL 0 Do nothing Seiko Epson Corporation AP-A-36 S1C33L26 TECHNICAL MANUAL...
Page 676 1 Always toggle 0 Normal toggle configuration 0) EnEndPoint 1 Enable endpoint 0 Disable endpoint – – – – 0 when being read. D3–0 EndPointNumber Endpoint number 0x0 R/W [3:0] (0x1 to 0xf) Seiko Epson Corporation AP-A-37 S1C33L26 TECHNICAL MANUAL...
Page 677 D7–2 – – – – 0 when being read. (Descriptor (8 bits) D1–0 DescSize[9:8] Descriptor size 0x0 R/W size high) DescSize_L 0x300c8b D7–0 DescSize[7:0] Descriptor size 0x0 R/W (Descriptor (8 bits) size low) Seiko Epson Corporation AP-A-38 S1C33L26 TECHNICAL MANUAL...
Page 678 Writing 0x96 removes the write W 0 when being read. Write Protect (16 bits) [15:0] protection of the WD_EN, WD_ Register CMP_L, and WD_CMP_H reg- (WD_ isters (0x301002–0x301006). PROTECT) Writing another value set the write protection. Seiko Epson Corporation AP-A-39 S1C33L26 TECHNICAL MANUAL...
Page 679 Control Register D7–1 – reserved – – – 0 when being read. (T8_INT0) T8IF T8 interrupt flag 1 Cause of 0 Cause of R/W Reset by writing 1. interrupt interrupt not occurred occurred Seiko Epson Corporation AP-A-40 S1C33L26 TECHNICAL MANUAL...
Page 680 T8 Ch.2 0x301124 D15–8 – reserved – – – 0 when being read. Counter Data (16 bits) D7–0 TC[7:0] T8 counter data 0x0 to 0xff 0xff Register TC7 = MSB (T8_TC2) TC0 = LSB Seiko Epson Corporation AP-A-41 S1C33L26 TECHNICAL MANUAL...
Page 681 Control Register D7–1 – reserved – – – 0 when being read. (T8_INT3) T8IF T8 interrupt flag 1 Cause of 0 Cause of R/W Reset by writing 1. interrupt interrupt not occurred occurred Seiko Epson Corporation AP-A-42 S1C33L26 TECHNICAL MANUAL...
Page 682 Count mode select 1 One shot 0 Repeat (T8_CTL5) D3–2 – reserved – – – 0 when being read. PRESER Timer reset 1 Reset 0 Ignored PRUN Timer run/stop control 1 Run 0 Stop Seiko Epson Corporation AP-A-43 S1C33L26 TECHNICAL MANUAL...
Page 683 T8 Ch.7 0x301174 D15–8 – reserved – – – 0 when being read. Counter Data (16 bits) D7–0 TC[7:0] T8 counter data 0x0 to 0xff 0xff Register TC7 = MSB (T8_TC7) TC0 = LSB Seiko Epson Corporation AP-A-44 S1C33L26 TECHNICAL MANUAL...
Page 684 A: ↑ or ↓ cmp A: ↑, B: ↓ D3–2 – reserved – – – 0 when being read. TOUTAINV TOUT A invert 1 Invert 0 Normal CCAMD T16A_CCA register mode select 1 Capture 0 Comparator Seiko Epson Corporation AP-A-45 S1C33L26 TECHNICAL MANUAL...
Page 685 W 0 when being read. PRUN Counter run/stop control 1 Run 0 Stop T16A5 Ch.1 0x301192 D15–0 T16ATC Counter data 0x0 to 0xffff Counter Data [15:0] (16 bits) T16ATC15 = MSB Register T16ATC0 = LSB (T16A_TC1) Seiko Epson Corporation AP-A-46 S1C33L26 TECHNICAL MANUAL...
Page 686 R/W Effective only for (T16P_VOL_ D6–0 VOLSEL Volume level select VOLSEL[6:0] Volume level 0x40 R/W 16-bit data CTL) [6:0] × 127/64 0x7f × 126/64 0x7e × 64/64 0x40 × 2/64 × 1/64 × 0 (mute) Seiko Epson Corporation AP-A-47 S1C33L26 TECHNICAL MANUAL...
Page 687 T8 Ch.2 Software – reserved – – – 0 when being read. D2–0 ADST[2:0] Sampling time setting ADST[2:0] Sampling time 0x7 R/W Always set to 0x7. 9•ADCCLK 8•ADCCLK 7•ADCCLK 6•ADCCLK 5•ADCCLK 4•ADCCLK 3•ADCCLK 2•ADCCLK Seiko Epson Corporation AP-A-48 S1C33L26 TECHNICAL MANUAL...
Page 688 0 when being read. Clock Division (16 bits) D5–0 MCLKDIV I2S_MCLK division ratio select MCLKDIV[5:0] Division ratio 0x0 R/W Source clock = Ratio Register [5:0] 0x3f 1/64 PCLK1 (I2S_DV_MCLK) 0x3e 1/63 0x3d 1/62 Seiko Epson Corporation AP-A-49 S1C33L26 TECHNICAL MANUAL...
Page 689 1/128 select 1/64 (Prescaler output clock) 1/32 1/16 D7–2 – reserved – – – 0 when being read. REMMD REMC mode select 1 Receive 0 Transmit REMEN REMC enable 1 Enable 0 Disable Seiko Epson Corporation AP-A-50 S1C33L26 TECHNICAL MANUAL...
Page 690 0 when being read. FPLINE_ FPLINE pulse polarity setup 1 Active high 0 Active low R/W (*1) D6–0 FPLINE_ FPLINE pulse width setup Pulse width = 0x0 R/W WD[6:0] FPLINE_WD + 1 [Ts] Seiko Epson Corporation AP-A-51 S1C33L26 TECHNICAL MANUAL...
Page 691 Areas 3*–5, 7–10, 13–16, and Table Base Ad- (32 bits) BADR[31:10] 19–22 be used. (1KB boundary address, A[9:0] = dress Register 0x0) (LCDC_ D9–0 – reserved – – – 0 when being read. RLDADR) Seiko Epson Corporation AP-A-52 S1C33L26 TECHNICAL MANUAL...
Page 692 D11–8 MLUT2[3:0] Monochrome LUT entry 2 data 0x0 to 0xf 0x0 R/W D7–4 MLUT1[3:0] Monochrome LUT entry 1 data 0x0 to 0xf 0x0 R/W D3–0 MLUT0[3:0] Monochrome LUT entry 0 data 0x0 to 0xf 0x0 R/W Seiko Epson Corporation AP-A-53 S1C33L26 TECHNICAL MANUAL...
Page 693 No hard trigger D3–2 TRG_SEL1 Ch.1 trigger select TRG_SEL1[1:0] Trigger source 0x0 R/W [1:0] Port No hard trigger D1–0 TRG_SEL0 Ch.0 trigger select TRG_SEL0[1:0] Trigger source 0x0 R/W [1:0] ADC complete T16P No hard trigger Seiko Epson Corporation AP-A-54 S1C33L26 TECHNICAL MANUAL...
Page 694 D2–0 ADDRC[2:0] SDRAM address configuration ADDRC[2:0] Configuration 0x0 R/W Do not set to 0x4. 512M bits 128M bits x 2 64M bits x 2 reserved 256M bits 128M bits 64M bits 16M bits Seiko Epson Corporation AP-A-55 S1C33L26 TECHNICAL MANUAL...
Page 695 4 cycles 1 cycle D5–4 CE4HOLD #CE4 hold cycle CE4HOLD[1:0] Hold cycle 0x3 R/W [1:0] 4 cycles 1 cycle D3–0 CE4WAIT #CE4 static wait cycle CE4WAIT[3:0] Wait cycle [3:0] 15 cycles 0 cycles Seiko Epson Corporation AP-A-56 S1C33L26 TECHNICAL MANUAL...
Page 696 (CCU_CFG) – reserved – – – Do not set to 1. SBRK Software break enable 1 Enable 0 Disable Instruction cache enable 1 Enable 0 Disable Data cache enable 1 Enable 0 Disable Seiko Epson Corporation AP-A-57 S1C33L26 TECHNICAL MANUAL...
Page 697 – 0 when being read. GE_ERR_ Drawing error interrupt enable 1 Enable 0 Disable D7–1 – reserved – – – 0 when being read. GE_ERR_ Calculation error interrupt enable 1 Enable 0 Disable Seiko Epson Corporation AP-A-58 S1C33L26 TECHNICAL MANUAL...
Page 698 0x0 R/W Register Y[11:0] Y coordinate (GE_CLIP_ D15–12 – reserved – – – 0 when being read. END) D11–0 CLIP_LWR_ Clipping area lower right corner 0 to 4,095 0x0 R/W X[11:0] X coordinate Seiko Epson Corporation AP-A-59 S1C33L26 TECHNICAL MANUAL...
Page 699 (User defined 2 to 4/8 bpp con- (GE_CCT1_ 0x302923 version data) 2BIT) (8 bits) CCT1 1-bit 0x302924 D7–0 – CCT1 data 0x0 to 0xff Entries (User defined 1 to 2/4/8 bpp con- (GE_CCT1_ 0x302925 version data) 1BIT) (8 bits) Seiko Epson Corporation AP-A-60 S1C33L26 TECHNICAL MANUAL...
Page 700 The CMU module provides a clock divider to set the system clock speed to 1/1 to 1/32 of the source clock (OSC3, PLL, OSC1). By running the S1C33L26 with the lowest speed required for the application’s task, current consumption can be reduced.
Page 701 The CPU resumes operating by occurrence of a cause of port input interrupt, #RESET, or #NMI. 2. Resuming by the RTC The CPU resumes operating by occurrence of a cause of RTC interrupt. Seiko Epson Corporation AP-B-2 S1C33L26 TECHNICAL MANUAL...
Page 702 Depending on the system configuration, the SLEEP mode may be efficient for saving power. Take these conditions into consideration at the system design stage. Seiko Epson Corporation AP-B-3 S1C33L26 TECHNICAL MANUAL...
Page 703 OSC1 output. Jitter in the OSC3 output will reduce operating frequencies, while noise in the OSC1 output will destabilize timers operated by the OSC1 clock as well as CPU Core operations when the system clock switches to OSC1. Seiko Epson Corporation AP-C-1 S1C33L26 TECHNICAL MANUAL...
Page 704 The receiver does not enter a floating state even when the USB cable is disconnected from the USB connec- tor. When the USB cable is disconnected, the VBUS pin is tied to V , so that leakage current will be the only source that drains power in the USB I/O block. Seiko Epson Corporation AP-C-2 S1C33L26 TECHNICAL MANUAL...
Page 705 Low-level noise to this pin will reset the IC. Depending on the input waveform, the reset may not proceed correctly. This is more likely to occur if, due to circuit design choices, the impedance is high when the reset input is high. Seiko Epson Corporation AP-C-3 S1C33L26 TECHNICAL MANUAL...
Page 706 (5) Adequate evaluations are required to assess nonvolatile memory data retention characteristics before prod- uct delivery if the product is subjected to heat stress exceeding regular reflow conditions during mounting processes. Seiko Epson Corporation AP-C-4 S1C33L26 TECHNICAL MANUAL...
Page 707 (2) Electromagnetically-induced noise from a solder iron when soldering In particular, during soldering, take care to ensure that the soldering iron GND (tip potential) has the same po- tential as the IC GND. Seiko Epson Corporation AP-C-5 S1C33L26 TECHNICAL MANUAL...
Page 708 (Either 8 bits or 16 bits) • SPI-EEPROM boot • PC RS232C boot The S1C33L26 boots up in the boot mode that can be selected with the BOOT and #CE10 pin configuration at ini- tial reset. Table D. 1.1 Boot Mode Setting...
Page 709 To boot up the system from a 16-bit NOR Flash/external ROM, write a reset vector in which the LSB is set to 0 to address 0x20000000. To boot up the system from an 8-bit NOR Flash/external ROM, write a reset vector in which the LSB is set to 1 to address 0x20000000. Seiko Epson Corporation AP-D-2 S1C33L26 TECHNICAL MANUAL...
Page 710 D.3.1 Configuration of SPI-EEPROM Boot System When the S1C33L26 is turned on or reset with the BOOT and #CE10 pins set to 1 (HV ), the S1C33L26 boots up by executing the MBR after loading it from the EEPROM, FRAM, or Serial Flash connected to the SPI bus to IRAM.
Page 711 EEPROM status. Waits for the EEPROM be ready status if it is busy. (4) Issues the READ command (0x03) with a 32-bit address (0x00 × 4 bytes) to the EEPROM. Seiko Epson Corporation AP-D-4 S1C33L26 TECHNICAL MANUAL...
Page 712 4-cycle address EEPROM Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 · · · Byte 512 · · · 512-byte executable code Figure D. 3.3.1 Data Location According to the EEPROM Size Seiko Epson Corporation AP-D-5 S1C33L26 TECHNICAL MANUAL...
Page 713 ) and the #CE10 pin set to 0 (V ), the S1C33L26 boots up by executing the MBR after loading it from the PC (RS232C) to IRAM via FSIO Ch.1. Figure D.4.1.1 shows a PC RS232C boot system connection diagram.
Page 714 FSIO Ch.1 is enabled with the calculated baud rate. (5) The S1C33L26 uploads a 4-byte chip ID code to the PC. The PC sends 512 bytes of executable codes to the S1C33L26 after the chip ID is verified. Seiko Epson Corporation...
Page 715 D.4.3 Transfer Data First the PC sends 4 bytes of 0x80 to the S1C33L26. Then the PC sends 512-byte MBR data after verifying the 4-byte chip ID code received from the S1C33L26. The S1C33L26 calculates the baud rate by counting the 4 bytes of 0x80 received from the PC and configures its serial interface.
Page 716 REVISION HISTORY Revision History Code No. Page Contents 411900100 New establishment 411900101 Features: SDRAMC (Old) • Equipped with a two-stage × 32-bit DQB (Data Queue Buffer). (New) • Equipped with a four-stage × 16-bit DQB (Data Queue Buffer). Features: USI/USIL (SPI mode) (Old) - Receive data mask function is available (master mode only).
Page 717: Table Of Contents
REVISION HISTORY Code No. Page Contents 411900101 10-7 SDRAMC: Initializing SDRAM (Old) 1. Initializing the SDRAMC registers ... (4) SDRAMC_APP register Set the CAS latency. Also enable the double frequency mode and queue buffer if necessary. (New) 1. Initializing the SDRAMC registers ... (4) SDRAMC_APP register Set the CAS latency.
Page 718 REVISION HISTORY Code No. Page Contents 411900101 18-19, 18-20 USI: Receive errors - Overrun error (Old) Overrun error (all interface modes) If data is received before the previously received data in the receive data buffer has not been read, ... The overrun error flag is reset to 0 by writing 1.
Page 719 REVISION HISTORY Code No. Page Contents 411900101 19-7 USIL: Receive data mask function (Old) Receive data mask function (master mode) The USIL in SPI master mode provides a receive data mask (data retransmission) function..For normal data transfer, set SMSKEN to 0 (default) to disable the receive data mask function. (New) Deleted 19-11 USIL: Data transfer in UART mode - Data reception...
Page 720 REVISION HISTORY Code No. Page Contents 411900101 19-28 USIL: Interrupts in UART mode - Receive error interrupt (Old) ... If any of the error flags has the value 1, ... proceed with error recovery. (New) ... If any of the error flags has the value 1, ... proceed with error recovery. To reset an overrun error, ...
Page 721 Boot: Configuration of SPI-EEPROM boot system (Old) When the S1C33L26 is turned on or reset with both the BOOT and #CE10 pins left open (or set to 1), ... (New) When the S1C33L26 is turned on or reset with the BOOT and #CE10 pins set to 1 (HV ), ...
Page 722 20/F, Harbour Centre, 25 Harbour Road, Wanchai, Hong Kong Phone: +852-2585-4600 Fax: +852-2827-4346 Telex: 65542 EPSCO HX EPSON TAIWAN TECHNOLOGY & TRADING LTD. 14F, No. 7, Song Ren Road, Taipei 110, TAIWAN Phone: +886-2-8786-6688 Fax: +886-2-8786-6660 EPSON SINGAPORE PTE., LTD.

Epson S1C33L26 Technical Manual

Quick Links

Related Manuals for Epson S1C33L26

Summary of Contents for Epson S1C33L26

Table of Contents