Operation Of Watchdog Timer - Fujitsu F2MC-8L Series Hardware Manual

6.4

Operation of Watchdog Timer

The watchdog timer generates a watchdog reset when the watchdog timer counter
overflows.
Watchdog Timer Operation
Activating watchdog timer
• The watchdog timer is activated by writing "0101
watchdog control register (WDTC: WTE3 to WTE0) for the first time after a reset. Specify the
count clock select bit (WDTC: CS) at the same time.
• Once activated, the watchdog timer cannot be stopped other than by a reset.
Clearing watchdog timer
• The watchdog timer counter is cleared by writing "0101
watchdog control register (WDTC: WTE3 to WTE0) for the second or subsequent times after
a reset.
• If the counter is not cleared within the interval time of the watchdog timer, the counter
overflows and the watchdog timer generates an internal reset signal for four-instruction
cycles.
Interval time of watchdog timer
The interval time changes depending on when the watchdog timer is cleared.
6.4 Operation of Watchdog Timer
" to the watchdog control bits in the
B
" to the watchdog control bits in the
B
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