Stop Mode - Fujitsu MB90460 Series Hardware Manual

CHAPTER 6 LOW POWER CONSUMPTION MODE
6.5.3

Stop Mode

Stop mode causes the source oscillation to stop and deactivates all functions. It
therefore saves the most power saving while data is being retained.
■ Switching to Stop Mode
Writing "1" to the STP bit of LPMCR triggers a switch to stop mode.
At this time, if the MCS bit of the clock selection register (CKSCR) is "0", the microcontroller enters PLL
stop mode. If the MCS bit of CKSCR is "1", the microcontroller enters main stop mode.
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Data retention function
In stop mode, the contents of dedicated registers, such as accumulators and internal RAM, are retained.
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Operation during an interrupt
Writing "1" to the STP bit of LPMCR during an interrupt request does not trigger switching to stop mode.
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Pin state setting
Selection of whether the external pins retain the state they had immediately before switching to stop mode
or go to high-impedance with switching to stop mode can be controlled by the SPL bit of LPMCR.
■ Release of Stop Mode
The low power consumption control circuit releases stop mode. The release is caused by input of a reset or
by an interrupt.
Because the oscillation of the operating clock is halted before return to normal mode from stop mode, the
low power consumption control circuit puts the microcontroller into the oscillation stabilization wait state,
then releases stop mode.
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Return to normal mode by a reset
When stop mode is released by a reset cause, the microcontroller is placed in the oscillation stabilization
wait and reset state after release from stop mode. The reset sequence proceeds after the oscillation
stabilization wait interval has elapsed.
●
Return to normal mode by a interrupt
If an interrupt request higher than level 7 is issued from a peripheral circuit during stop mode (when IL2,
IL1 and IL0 of the interrupt control register (ICR) are set to a value other than "111
consumption control circuit releases stop mode. After release, the CPU handles the interrupt as it would
any other interrupts. However, the CPU starts after the main clock oscillation stabilization wait interval
specified by the WS1 and WS0 bits of the clock selection register (CKSCR) has elapsed. The CPU
executes processing according to the settings of the I flag of the condition code register (CCR), interrupt
level mask register (ILM), and interrupt control register (ICR). If the interrupt is accepted, the CPU
executes interrupt processing. If the interrupt is not accepted, the CPU resumes the execution with the
instruction that follows the instruction in which switching to stop mode was specified.
104
), the low power
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