Pc Break Operation At Consecutive Data Transfer; Operation In Transitions To Power-Down Modes; Figure 6.2 Operation In Power-Down Mode Transitions - Hitachi H8S/2628 Hardware Manual

6.3.3

PC Break Operation at Consecutive Data Transfer

• When a PC break interrupt is generated at the transfer address of an EEPMOV.B instruction
PC break exception handling is executed after all data transfers have been completed and the
EEPMOV.B instruction has ended.
• When a PC break interrupt is generated at a DTC transfer address
PC break exception handling is executed after the DTC has completed the specified number of
data transfers, or after data for which the DISEL bit is set to 1 has been transferred.
6.3.4

Operation in Transitions to Power-Down Modes

The operation when a PC break interrupt is set for an instruction fetch at the address after a
SLEEP instruction is shown below.
• When the SLEEP instruction causes a transition from high-speed (medium-speed) mode to
sleep mode:
After execution of the SLEEP instruction, a transition is not made to sleep mode, and PC break
exception handling is executed. After execution of PC break exception handling, the
instruction at the address after the SLEEP instruction is executed (figure 6.2 (A)).
• When the SLEEP instruction causes a transition to software standby mode:
After execution of the SLEEP instruction, a transition is made to software standby mode, and
PC break exception handling is not executed. However, the CMFA or CMFB flag is set (figure
6.2 (B)).

Figure 6.2 Operation in Power-Down Mode Transitions

SLEEP
instruction execution
PC break exception
handling
Execution of instruction
after sleep instruction
(A)
SLEEP instruction
execution
Transition to
respective mode
(B)
Rev. 1.0, 09/02, page 89 of 568