Interrupt Mask Register (Imr) - Hitachi H8S/2628 Hardware Manual

15.3.13 Interrupt Mask Register (IMR)

IMR is a 16-bit register containing flags that enable or disable requests by individual interrupt
sources. The reset interrupt flag cannot be masked.
Bit Bit Name
15 IMR7
14 IMR6
13 IMR5
12 IMR4
11 IMR3
10 IMR2
9 IMR1

8

7 to
5
Initial Value R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
0 R
All 1 R
Description
Overload Frame Interrupt Mask
When this bit is cleared to 0, an interrupt request
by IRR7 (OVR0) is enabled. When set to 1, it is
masked.
Bus Off Interrupt Mask
When this bit is cleared to 0, an interrupt request
by IRR6 (ERS0) is enabled. When set to 1, it is
masked.
Error Passive Interrupt Mask
When this bit is cleared to 0, an interrupt request
by IRR5 (ERS0) is enabled. When set to 1, it is
masked.
Receive Overload Warning Interrupt Mask
When this bit is cleared to 0, an interrupt request
by IRR4 (OVR0) is enabled. When set to 1, it is
masked.
Transmit Overload Warning Interrupt Mask
When this bit is cleared to 0, an interrupt request
by IRR3 (OVR0) is enabled. When set to 1, it is
masked.
Remote Frame Request Interrupt Mask
When this bit is cleared to 0, an interrupt request
by IRR2 (OVR0) is enabled. When set to 1, it is
masked.
Receive Message Interrupt Mask
When this bit is cleared to 0, an interrupt request
by IRR1 (RM1) is enabled. When set to 1, it is
masked.
Reserved
This bit is always read as 0. The write value should
always be 0.
Reserved
These bits are always read as 1. The write value
should always be 0.
Rev. 1.0, 09/02, page 375 of 568