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Bit
Bit Name
7 to
4
3
NDR11
2
NDR10
1
NDR9
0
NDR8
• NDRL
If pulse output groups 0 and 1 have the same output trigger, all eight bits are mapped to the same
address and can be accessed at one time, as shown below.
Bit
Bit Name
7
NDR7
6
NDR6
5
NDR5
4
NDR4
3
NDR3
2
NDR2
1
NDR1
0
NDR0
If pulse output groups 0 and output pulse groups 1 have different output triggers, upper 4 bits and
lower 4 bits are mapped to the different addresses as shown below.
Bit
Bit Name
7
NDR7
6
NDR6
5
NDR5
4
NDR4
3 to
0
Initial Value
R/W
All 1
0
R/W
0
R/W
0
R/W
0
R/W
Initial Value
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Initial Value
R/W
0
R/W
0
R/W
0
R/W
0
R/W
All 1
Description
Reserved
These bits are always read as 1 and cannot be
modified.
Next Data Register 8 to11
The register contents are transferred to the
corresponding PODRH bits by the output trigger
specified with PCR.
Description
Next Data Register 0 to 7
The register contents are transferred to the
corresponding PODRL bits by the output trigger
specified with PCR.
Description
Next Data Register 4 to 7
The register contents are transferred to the
corresponding PODRL bits by the output trigger
specified with PCR.
Reserved
These bits are always read as 1 and cannot be
modified.
Rev. 1.0, 09/02, page 269 of 568
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