Conflict Between Tgr Write And Input Capture; Figure 10.50 Conflict Between Tgr Write And Input Capture - Hitachi H8S/2628 Hardware Manual

10.9.9

Conflict between TGR Write and Input Capture

If an input capture signal is generated in the T2 state of a TGR write cycle, the input capture
operation takes precedence and the write to TGR is not performed.
Figure 10.50 shows the timing in this case.
φ
Address
Write signal
Input capture
signal
TCNT
TGR

Figure 10.50 Conflict between TGR Write and Input Capture

TGR write cycle
T1 T2
TGR address
M
M
Rev. 1.0, 09/02, page 237 of 568