Hitachi H8S/2628 Hardware Manual page 16

12.4.4 Example of Normal Pulse Output (Example of Five-Phase Pulse Output).......... 275
12.4.5 Non-Overlapping Pulse Output............................................................................ 276
12.4.6 Sample Setup Procedure for Non-Overlapping Pulse Output .............................. 278
12.4.7 Example of Non-Overlapping Pulse Output
(Example of Four-Phase Complementary Non-Overlapping Output).................. 279
12.4.8 Inverted Pulse Output .......................................................................................... 281
12.4.9 Pulse Output Triggered by Input Capture ............................................................ 282
12.5 Usage Notes ...................................................................................................................... 282
12.5.1 Module Stop Mode Setting .................................................................................. 282
12.5.2 Operation of Pulse Output Pins............................................................................ 282
Section 13 Watchdog Timer ..............................................................................283
13.1 Features............................................................................................................................. 283
13.2 Register Descriptions ........................................................................................................ 284
13.2.1 Timer Counter (TCNT)........................................................................................ 284
13.2.2 Timer Control/Status Register (TCSR)................................................................ 284
13.2.3 Reset Control/Status Register (RSTCSR) ............................................................ 286
13.3 Operation .......................................................................................................................... 287
13.3.1 Watchdog Timer Mode Operation ....................................................................... 287
13.3.2 Interval Timer Mode............................................................................................ 287
13.4 Interrupts........................................................................................................................... 288
13.5 Usage Notes ...................................................................................................................... 288
13.5.1 Notes on Register Access..................................................................................... 288
13.5.2 Conflict between Timer Counter (TCNT) Write and Increment.......................... 289
13.5.3 Changing Value of CKS2 to CKS0...................................................................... 290
13.5.4 Switching between Watchdog Timer Mode and Interval Timer Mode................ 290
13.5.5 Internal Reset in Watchdog Timer Mode............................................................. 290
13.5.6 OVF Flag Clearing in Interval Timer Mode ........................................................ 290
Section 14 Serial Communication Interface (SCI) ............................................291
14.1 Features............................................................................................................................. 291
14.2 Input/Output Pins .............................................................................................................. 293
14.3 Register Descriptions ........................................................................................................ 293
14.3.1 Receive Shift Register (RSR) .............................................................................. 294
14.3.2 Receive Data Register (RDR) .............................................................................. 294
14.3.3 Transmit Data Register (TDR)............................................................................. 294
14.3.4 Transmit Shift Register (TSR) ............................................................................. 294
14.3.5 Serial Mode Register (SMR) ............................................................................... 295
14.3.6 Serial Control Register (SCR).............................................................................. 299
14.3.7 Serial Status Register (SSR) ................................................................................ 302
14.3.8 Smart Card Mode Register (SCMR) .................................................................... 307
14.3.9 Bit Rate Register (BRR) ...................................................................................... 308
14.4 Operation in Asynchronous Mode .................................................................................... 315
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