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16.4
Operation
16.4.1
Transfer Clock
A transfer clock can be selected from eight internal clocks and an external clock. When using this
module, set SCKS in SSCRH to 1 to select the SSCK pin as a serial clock. When MSS in SSCRH
is 1, an internal clock is selected and the SSCK pin is used as an output pin. When transfer is
started, the clock with the transfer rate set by bits CKS2 to CKS0 in SSMR is output from the
SSCK pin. When MSS = 0, an external clock is selected and the SSCK pin is used as an input pin.
16.4.2
Relationship of Clock Phase, Polarity, and Data
The relationship of clock phase, polarity, and transfer data depends on the combination of CPOS
and CPHS in SSMR. Figure 16.2 shows the relationship.
Setting the MLS bit specifies that MSB or LSB first communication. When MLS = 0, data is
transferred from the LSB to MSB. When MLS = 1, data is transferred from the MSB to LSB.
(1) When CPHS = 0
SSCK
(CPOS = 0)
SSCK
(CPOS = 1)
SSI, SSO
(2) When CPHS = 1
SSCK
(CPOS = 0)
SSCK
(CPOS = 1)
SSI, SSO
Figure 16.2 Relationship of Clock Phase, Polarity, and Data
16.4.3
Relationship between Data I/O Pins and the Shift Register
The connection between data I/O pins and the shift register (SSTRSR) depends on the
combination of the MSS and BIDE bits in SSCRH. The data input pin and data output pin can be
set independently by the values of TE and RE.
Rev. 1.0, 09/02, page 416 of 568
Bit 0
Bit 1
Bit 2
Bit 0
Bit 1
Bit 2
Bit 3
Bit 3
Bit 4
Bit 5
Bit 6
Bit 4
Bit 5
Bit 6
Bit 7
Bit 7
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