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15.4.6
HCAN Halt Mode
The HCAN halt mode is provided to enable mailbox settings to be changed without performing an
HCAN hardware or software reset. Figure 15.14 shows a flowchart of the HCAN halt mode.
HCAN halt mode is entered by setting the halt request bit (MCR1) to 1 in the master control
register (MCR). If the CAN bus is operating, the transition to HCAN halt mode is delayed until
the bus becomes idle.
HCAN halt mode is cleared by clearing MCR1 to 0.
MCR1 = 1
Bus idle?
Yes
Set MBCR
MCR1 = 0
CAN bus communication possible
Figure 15.14 HCAN Halt Mode Flowchart
No
: Settings by user
: Processing by hardware
Rev. 1.0, 09/02, page 399 of 568
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