Block Transfer Mode; Figure 8.7 Memory Mapping In Block Transfer Mode; Table 8.4 Register Information In Block Transfer Mode - Hitachi H8S/2628 Hardware Manual

8.5.3

Block Transfer Mode

In block transfer mode, one operation transfers one block of data. Either the transfer source or the
transfer destination is designated as a block area. Table 8.4 lists the register information in block
transfer mode.
The block size can be between 1 and 256. When the transfer of one block ends, the initial state of
the block size counter and the address register specified as the block area is restored. The other
address register is then incremented, decremented, or left fixed.
From 1 to 65,536 transfers can be specified. Once the specified number of transfers have been
completed, a CPU interrupt is requested.
Table 8.4 Register Information in Block Transfer Mode
Name
DTC source address register
DTC destination address register
DTC transfer count register AH
DTC transfer count register AL
DTC transfer count register B
SAR
or
DAR

Figure 8.7 Memory Mapping in Block Transfer Mode

Abbreviation
SAR
DAR
CRAH
CRAL
CRB
First block
Transfer
Nth block
Function
Designates source address
Designates destination address
Holds block size
Designates block size count
Transfer count
Block area
Rev. 1.0, 09/02, page 111 of 568
DAR
or
SAR