Conflict Between Interrupts And Module Stop Mode; Notes On Cascaded Connection - Hitachi H8S/2628 Hardware Manual

Timing of Switchover
by Means of CKS1
No. and CKS0 Bits
3 Switching from high
3
to low*
4 Switching from high
to high
Notes: 1. Includes switching from low to stop, and from stop to low.
2. Includes switching from stop to high.
3. Includes switching from high to stop.
4. Generated on the assumption that the switchover is a falling edge; TCNT is
incremented.
11.8.6

Conflict between Interrupts and Module Stop Mode

If module stop mode is entered when an interrupt has been requested, it will not be possible to
clear the CPU interrupt source or the DTC activation source. Interrupts should therefore be
disabled before entering module stop mode.
11.8.7

Notes on Cascaded Connection

If 16-bit count mode and compare-match count mode are set simultaneously, the counter stops and
does not operate since input clocks of TCNT_0 and TCNT_1 (TCNT_2 and TCNT_3) are not
generated. This setting is inhibited.
Rev. 1.0, 09/03, page 262 of 568
TCNT Clock Operation
Clock before
switchover
Clock after
switchover
TCNT clock
TCNT N
φ
TCNT input
clock
TCNT H'FFFF
Counter
clear signal
TGF
Disabled
TCFV
4
*
N + 1 N + 2
CKS bit rewrite
H'0000