Pwm Modes; Figure 10.18 Example Of Cascaded Operation (1); Figure 10.19 Example Of Cascaded Operation (2) - Hitachi H8S/2628 Hardware Manual

TCNT_1
clock
TCNT_1 H'03A1
TCNT_2
clock
TCNT_2 H'FFFF
TIOCA1,
TIOCA2
TGRA_1
TGRA_2
Figure 10.19 illustrates the operation when TCNT_2 overflow/underflow counting has been set for
TCNT_1 and phase counting mode has been designated for channel 2.
TCNT_1 is incremented by TCNT_2 overflow and decremented by TCNT_2 underflow.
TCLKA
TCLKB
TCNT_2
TCNT_1
10.4.5

PWM Modes

In PWM mode, PWM waveforms are output from the output pins. The output level can be selected
as 0, 1, or toggle output in response to a compare match of each TGR.
TGR registers settings can be used to output a PWM waveform in the range of 0% to 100% duty
cycle.
Designating TGR compare match as the counter clearing source enables the period to be set in that
register. All channels can be designated for PWM mode independently. Synchronous operation is
also possible.
H'0000

Figure 10.18 Example of Cascaded Operation (1)

FFFD FFFE FFFF 0000
0000

Figure 10.19 Example of Cascaded Operation (2)

H'03A2
H'03A2
H'0000
0001 0002 0001
0001
Rev. 1.0, 09/02, page 209 of 568
H'0001
0000 FFFF
0000