Figure 16.1 Block Diagram Of Ssu - Hitachi H8S/2628 Hardware Manual

Figure 16.1 shows a block diagram of the SSU.
SSTDR 0
SSTDR 1
SSTDR 2
SSTDR 3
SSI
[Legend]
SSCRH
SSCRL
SSMR
SSER
SSSR
SSTDR0 to SSTDR3
SSRDR0 to SSRDR3
SSTRSR
Rev. 1.0, 09/02, page 406 of 568
Module data bus
SSRDR 0
SSRDR 1
SSRDR 2
SSRDR 3
SSTRSR
Selector
SSO
: SS control register H
: SS control register L
: SS mode register
: SS enable register
: SS status register
: SS transmit data register
: SS receive data register
: SS transmit/recive shift register

Figure 16.1 Block Diagram of SSU

SSCRH
SSCRL
SSMR
SSER
SSSR
Control circuit
Clock
Clock
selector
SSCK (External clock)
Internal data bus
OEI
CEI
RXI
TXI
TEI
φ
φ/2
φ/4
φ/8
φ/16
φ/32
φ/64
φ/128
φ/256