Table of Contents
Advertisement
Register Name
SS enable register_1
SS status register_1
SS transmit data register 0_1
SS transmit data register 1_1
SS transmit data register 2_1
SS transmit data register 3_1
SS receive data register 0_1
SS receive data register 1_1
SS receive data register 2_1
SS receive data register 3_1
Port D realtime input data register PDRTIDR
Timer control register_2
Timer control register_3
Timer control/status register_2
Timer control/status register_3
Timer constant register A_2
Timer constant register A_3
Timer constant register B_2
Timer constant register B_3
Timer counter_2
Timer counter_3
Standby control register
System control register
System clock control register
Mode control register
Module stop control register A
Module stop control register B
Module stop control register C
Low-power control register
Break address register A
Break address register B
Break control register A
Break control register B
IRQ sense control register H
Number
Abbreviation
of Bits
SSER_1
8
SSSR_1
8
SSTDR0_1 8
SSTDR1_1 8
SSTDR2_1 8
SSTDR3_1 8
SSRDR0_1 8
SSRDR1_1 8
SSRDR2_1 8
SSRDR3_1 8
8
TCR_2
8
TCR_3
8
TCSR_2
8
TCSR_3
8
TCORA_2
8
TCORA_3
8
TCORB_2
8
TCORB_3
8
TCNT_2
8
TCNT_3
8
SBYCR
8
SYSCR
8
SCKCR
8
MDCR
8
MSTPCRA 8
MSTPCRB 8
MSTPCRC 8
LPWRCR
8
BARA
32
BARB
32
BCRA
8
BCRB
8
ISCRH
8
Address*
Module
H'FB13
SSU_1
H'FB14
SSU_1
H'FB16
SSU_1
H'FB17
SSU_1
H'FB18
SSU_1
H'FB19
SSU_1
H'FB1A
SSU_1
H'FB1B
SSU_1
H'FB1C
SSU_1
H'FB1D
SSU_1
H'FB40
PORT
H'FDC0
TMR_2
H'FDC1
TMR_3
H'FDC2
TMR_2
H'FDC3
TMR_3
H'FDC4
TMR_2
H'FDC5
TMR_3
H'FDC6
TMR_2
H'FDC7
TMR_3
H'FDC8
TMR_2
H'FDC9
TMR_3
H'FDE4
SYSTEM 8
H'FDE5
SYSTEM 8
H'FDE6
SYSTEM 8
H'FDE7
SYSTEM 8
H'FDE8
SYSTEM 8
H'FDE9
SYSTEM 8
H'FDEA
SYSTEM 8
H'FDEC
SYSTEM 8
H'FE00
PBC
H'FE04
PBC
H'FE08
PBC
H'FE09
PBC
H'FE12
INT
Rev. 1.0, 09/02, page 503 of 568
Data
Access
Width
State
16
3
16
3
16
3
16
3
16
3
16
3
16
3
16
3
16
3
16
3
8
3
8
2
8
2
8
2
8
2
8
2
8
2
8
2
8
2
8
2
8
2
2
2
2
2
2
2
2
2
32
2
32
2
8
2
8
2
8
2
Advertisement
Table of Contents
