Hitachi H8S/2628 Hardware Manual page 450

Bit Bit Name
0 CE
Rev. 1.0, 09/02, page 414 of 568
Initial Value R/W
0 R/W
Description
Conflict/Incomplete Error
Indicates that a conflict error has occurred when 0
is externally input via the SCS pin with MSS = 1.
If the SCS pin level changes to 1 during slave
operation, an incomplete error occurs because it
is determined that a master device has terminated
the transfer. Data reception does not continue
while the CE bit is set to 1. Reset the SSU internal
sequencer by setting the SRES bit in SSCRL to 1
before resuming transfer after incomplete error.
[Setting condition]
When a low level is input to the SCS pin in
•
master device mode (MSS in SSCRH = 1)
When a 1 is input to the SCS pin during slave
•
device mode (MSS in SSCRH = 0) transfer
[Clearing condition]
•
When 0 is written to the CE bit after reading
CE = 1