Figure 16.4 Example Of Ssu Initialization - Hitachi H8S/2628 Hardware Manual

Clear TE and RE bits in SSER to 0
[1] Specify CSS1, CSS0, MSS, BIDE, SOL,
[2] Specify bits DATS1 and DATS0
[3] Specify CKS2 to CKS0, MLS, CPOS,
[4]
• Data Transmission
Figure 16.5 shows an example of transmission operation, and figure 16.6 shows an example of
data transmission flowchart.
When transmitting data, the SSU operates as shown below.
In master device mode, the SSU outputs a transfer clock and data. In slave device mode, when a
low level signal is input to the SCS pin and a transfer clock is input to the SSCK pin, the SSU
outputs data in synchronization with the transfer clock.
Writing transmit data to SSTDR after the TE bit is set to 1 clears the TDRE bit to 0, and the
SSTDR contents is transferred to SSTRSR. After that, the SSU sets the TDRE bit to 1 and starts
transmission. At this time, if the TIE bit in SSER is set to 1, a TXI interrupt is generated.
When 1-frame data has been transferred with the TDRE bit cleared to 0, the SSTDR contents are
transferred to SSTRSR to start the next transmission. When the 8th bit of transmit data has been
transferred with the TDRE bit set to 1, the TEND bit in SSSR is set to 1 and the state is retained.
At this time, if the TEIE bit is set to 1, a TEI interrupt is generated. After transmission, the output
level of the SSCK pin is fixed at a high level when CPOS = 0 and at a low level when CPOS = 1.
While the ORER bit in SSSR is set to 1, transmission is not performed. Check that the ORER bit
is cleared to 0.
Rev. 1.0, 09/02, page 418 of 568
Start initialization
and SCKS bits
and CPHS bits
SpecifyTEIE, TIE, RIE,
and CEIE bits
End

Figure 16.4 Example of SSU Initialization

[1] Specify master/slave device selection,
bidirectional mode enable, SSO pin
output value selection, SSCK pin selection,
and SCS pin selection.
[2] Specify transmit/receive data length.
[3] Specify MSB first/LSB first selection, clock
polarity selection, clock phase selection,
and transfer clock rate selection.
[4] Specify enable/disable of interrupt request
to the CPU.