Hitachi H8S/2628 Hardware Manual page 284

Initial
Bit Bit Name Value
3 OS3 0
2 OS2 0
1 OS1 0
0 OS0 0
Note:* Only a 0 can be written to this bit, to clear the flag
Rev. 1.0, 09/03, page 248 of 568
R/W Description
R/W Output Select 3 and 2
R/W These bits specify how the timer output level is to be
changed by a compare-match B of TCORB and
TCNT.
00: No change when compare-match B occurs
01: 0 is output when compare-match B occurs
10: 1 is output when compare-match B occurs
11: Output is inverted when compare-match B occurs
(toggle output)
R/W Output Select 1 and 0
R/W These bits specify how the timer output level is to be
changed by a compare-match A of TCORA and
TCNT.
00: No change when compare-match A occurs
01: 0 is output when compare-match A occurs
10: 1 is output when compare-match A occurs
11: Output is inverted when compare-match A occurs
(toggle output)