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Table 8.5
DTC Execution Status
Vector Read
Mode
I
Normal
1
Repeat
1
Block transfer
1
Legend
N: Block size (initial setting of CRAH and CRAL)
Table 8.6
Number of States Required for Each Execution Status
Object to be Accessed
Bus width
Access states
Execution
Vector read S
status
Register information
read/write S
Byte data read S
Word data read S
Byte data write S
Word data write S
Internal operation S
Note:* Not available in this LSI.
The number of execution states is calculated from using the formula below. Note that Σ is the sum
of all transfers activated by one activation source (the number in which the CHNE bit is set to 1,
plus 1).
Number of execution states = I · (1 + S
For example, when the DTC vector address table is located in the on-chip ROM, normal mode is
set, and data is transferred from on-chip ROM to an internal I/O register, then the time required for
the DTC operation is 13 states. The time from activation to the end of the data write is 10 states.
Register Information
Read/Write
J
6
6
6
On-
Chip
RAM
32
1
I
1
J
1
K
1
K
1
L
1
L
1
M
) + Σ (J · S
I
Data Read
K
1
1
N
On-
Chip
On-Chip I/O
ROM
Registers
16
8
16
1
2
2
1
1
2
2
1
4
2
1
2
2
1
4
2
+ K · S
+ L · S
J
K
L
Rev. 1.0, 09/02, page 115 of 568
Internal
Data Write
Operations
L
M
1
3
1
3
N
3
External Devices*
8
16
2
3
2
4
6+2m 2
2
3+m
2
4
6+2m 2
2
3+m
2
4
6+2m 2
) + M · S
M
3
3+m
3+m
3+m
3+m
3+m
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