Hitachi H8S/2628 Hardware Manual page 20

19.1 Features............................................................................................................................. 445
19.2 Mode Transitions .............................................................................................................. 446
19.3 Block Configuration.......................................................................................................... 450
19.4 Input/Output Pins .............................................................................................................. 451
19.5 Register Descriptions ........................................................................................................ 451
19.5.1 Flash Memory Control Register 1 (FLMCR1)..................................................... 452
19.5.2 Flash Memory Control Register 2 (FLMCR2)..................................................... 453
19.5.3 Erase Block Register 1 (EBR1) ........................................................................... 453
19.5.4 Erase Block Register 2 (EBR2) ........................................................................... 454
19.5.5 RAM Emulation Register (RAMER)................................................................... 454
19.6 On-Board Programming Modes........................................................................................ 455
19.6.1 Boot Mode ........................................................................................................... 456
19.6.2 Programming/Erasing in User Program Mode..................................................... 458
19.7 Flash Memory Emulation in RAM ................................................................................... 459
19.8 Flash Memory Programming/Erasing ............................................................................... 461
19.8.1 Program/Program-Verify ..................................................................................... 461
19.8.2 Erase/Erase-Verify............................................................................................... 463
19.8.3 Interrupt Handling when Programming/Erasing Flash Memory.......................... 463
19.9 Program/Erase Protection ................................................................................................. 465
19.9.1 Hardware Protection ............................................................................................ 465
19.9.2 Software Protection.............................................................................................. 465
19.9.3 Error Protection.................................................................................................... 465
19.10 Programmer Mode ............................................................................................................ 466
19.11 Power-Down States for Flash Memory............................................................................. 466
Section 20 Clock Pulse Generator .....................................................................467
20.1 Register Descriptions ........................................................................................................ 468
20.1.1 System Clock Control Register (SCKCR) ........................................................... 468
20.1.2 Low-Power Control Register (LPWRCR) ........................................................... 469
20.2 Oscillator........................................................................................................................... 470
20.2.1 Connecting a Crystal Resonator........................................................................... 470
20.2.2 External Clock Input............................................................................................ 471
20.3 PLL Circuit ....................................................................................................................... 473
20.4 Medium-Speed Clock Divider .......................................................................................... 473
20.5 Bus Master Clock Selection Circuit.................................................................................. 473
20.6 Usage Notes ...................................................................................................................... 474
20.6.1 Note on Crystal Resonator ................................................................................... 474
20.6.2 Note on Board Design.......................................................................................... 474
Section 21 Power-Down Modes ........................................................................477
21.1 Register Descriptions ........................................................................................................ 480
21.1.1 Standby Control Register (SBYCR) .................................................................... 480
21.1.2 Module Stop Control Registers A to C (MSTPCRA to MSTPCRC)................... 482
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