Figure 16.7 Example Of Reception Operation - Hitachi H8S/2628 Hardware Manual

(1) When 8-bit data length is selected (SSRDR0 is valid) with CPOS = 0 and CPHS 0
SSCK
SSI
RDRF
LSI operation
User operation
(2) When 16-bit data length is selected (SSRDR0 and SSRDR1 are valid) with CPOS = 0 and CPHS 0
SSCK
SSO
(LSB first)
SSO
(MSB first)
RDRF
LSI operation
User operation
(3) When 32-bit data length is selected (SSRDR0 and SSRDR3 are valid) with CPOS = 0 and CPHS 0
SSCK
SSO
(LSB first)
SSO
(MSB first)
RDRF
LSI operation
User operation
Rev. 1.0, 09/02, page 422 of 568
1 frame
Bit Bit Bit Bit Bit
0 1 2 3 4
SSTDR0 (LSB first transmission)
Dummy-read
SSRDR0
Bit Bit Bit Bit Bit
0 1 2 3 4
SSRDR1
Bit Bit Bit Bit Bit
7 6 5 4 3
SSRDR0
Dummy-read
SSRDR0
1 frame
Bit Bit Bit
to to
0 7 0
SSRDR3 SSRDR2
Bit Bit Bit
to to
7 0 7
SSRDR0 SSRDR1
Dummy-read
SSRDR0

Figure 16.7 Example of Reception Operation

Bit Bit Bit Bit Bit
5 6 7 7 6
SSTDR0 (MSB first transmission)
RXI
interrupt
generated
Read SSRDR0
1 frame
Bit Bit Bit
Bit Bit Bit Bit
5 6 7 0 1 2 3
SSRDR0
Bit Bit Bit Bit Bit Bit Bit
7 6 5 4
2 1 0
SSRDR1
Bit Bit Bit Bit Bit
to to
7 0 7 0 7
SSRDR1 SSRDR0
Bit Bit Bit Bit Bit
to to
0 7 0 7 0
SSRDR2 SSRDR3
RXI
interrupt
generated
1 frame
Bit Bit Bit Bit Bit Bit
5 4 3 2 1 0
RXI
interrupt
generated
Bit Bit Bit Bit
4 5 6 7
Bit Bit Bit Bit
3 2 1 0
RXI
interrupt
generated