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[1]
TE = 1 (transmission enabled)
[2]
Read TDRE in SSR
Write transmit data to SSTDR
TDRE automatically cleared
Data transferd from SSTDR to SSTRSR
Set TDRE to 1 to start transmission
[3]
Continuous data transmission?
Read TEND in SSSR
Clear TEND to 0
Clear TE in SSER to 0
End transmission
Note: Hatching boxes represent SSU internal operations.
Figure 16.6 Example of Data Transmission Flowchart
• Data Reception
Figure 16.7 shows an example of reception operation, and figure 16.8 shows an example of data
reception flowchart.
When receiving data, the SSU operates as shown below.
After the SSU sets the RE bit to 1 and dummy-reads SSRDR, data reception is started.
In master device mode, the SSU outputs a transfer clock and receives data. In slave device mode,
when a low level signal is input to the SCS pin and a transfer clock is input to the SSCK pin, the
SSU receives data in synchronization with the transfer clock.
When 1-frame data has been received, the received data is stored in SSRDR. At this time, if the
RIE bit is set to 1, an RXI interrupt is generated. The RDRF bit is automatically cleared to 0 by
reading SSRDR.
Rev. 1.0, 09/02, page 420 of 568
Start
Initialization
No
TDRE = 1?
Yes
Yes
No
No
TEND = 1?
Yes
[1] Initialization:
Specify the settings such as transmit
data format.
[2] Check tha SSU state and write
transmit data:
Write transmit data to SSTDR after
reading and confirming that the TDRE bit
is 1. THe TDRE bit is automaticallu cleared
to 0 and transmission is started by writing
data to SSTDR.
[3] Procedure for continuous data transmission:
To continue data transmission, confirm
that the TDRE bit is 1 meaning tha SSTDR
is ready to be written to. After that, data can
be written to SSTDR. The TDRE bit is
automatically cleared to 0 by writing data to
SSTDR.
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