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16.3.6
SS Transmit Data Register 0 to 3 (SSTDR0 to SSTDR3)
SSTDR is an 8-bit register that stores transmit data. When 8-bit data length is selected by bits
DATS1 and DATS0 in SSCRL, SSTDR0 is valid. When 16-bit data length is selected, SSTDR0
and SSTDR1 are valid. When 32-bit data length is selected, SSTDR0 to SSTDR3 are valid.
When the SSU detects that SSTRSR is empty, it transfers the transmit data written in SSTDR to
SSTRSR and starts transmission. If the next transmit data has already been written to SSTDR
during serial transmission, the SSU transfers the written data to SSTRSR to continue transmission.
Although SSTDR can be read or written to by the CPU and DTC at all times, to achieve reliable
serial transmission, write transmit data to SSTDR after confirming that the TDRE bit in SSSR is
set to 1. The initial value of this register is H'00.
16.3.7
SS Receive Data Register 0 to 3 (SSRDR0 to SSRDR3)
SSRDR is an 8-bit register that stores receive data. When 8-bit data length is selected by bits
DATS1 and DATS0 in SSCRL, SSRDR0 is valid. When 16-bit data length is selected, SSRDR0
and SSRDR1 are valid. When 32-bit data length is selected, SSRDR0 to SSRDR3 are valid.
When the SSU has received 1-byte data, it transfers the received serial data from SSTRSR to
SSRDR where it is stored. After this, SSTRSR is receive-enabled. Since SSTRSR and SSRDR
function as a double buffer in this way, continuous receive operations can be performed. Read
SSRDR after confirming that the RDRF bit in SSSR is set to 1. SSRDR cannot be written to by
the CPU. The initial value of this register is H'00.
16.3.8
SS Shift Register (SSTRSR)
SSTRSR is a shift register that transmits and receives serial data.
When data from SSTDR to SSTRSR is transferred with MLS = 0, bit 0 of transmit data is bit 0 in
the SSTDR contents (LSB first communication). When data from SSTDR to SSTRSR is
transferred with MLS = 1, bit 0 of transmit data is bit 7 in the SSTDR contents (MSB first
communication). To perform serial data transmission, the SSU transfers data starting from LSB
(bit 0) in SSTRSR to the SSO pin.
In reception, the SSU sets serial data that has been input from the SSI pin to SSTRSR starting
from LSB (bit 0) and converts it into parallel data. When 1-byte data has been received, the
SSTRSR contents are automatically transferred to SSRDR. SSTRSR cannot be directly accessed
by the CPU.
Rev. 1.0, 09/02, page 415 of 568
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