Usage Notes; Conflict Between Tcnt Write And Clear; Conflict Between Tcnt Write And Increment; Figure 11.10 Conflict Between Tcnt Write And Clear - Hitachi H8S/2628 Hardware Manual

11.8

Usage Notes

11.8.1

Conflict between TCNT Write and Clear

If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the clear
takes priority, so that the counter is cleared and the write is not performed. Figure 11.10 shows
this operation.
φ
Address
Internal write signal
Counter clear signal
TCNT

Figure 11.10 Conflict between TCNT Write and Clear

11.8.2

Conflict between TCNT Write and Increment

If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the write
takes priority and the counter is not incremented. Figure 11.11 shows this operation.
Rev. 1.0, 09/03, page 258 of 568
TCNT write cycle by CPU
T T
1 2
TCNT address
N H'00