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Section 6 PC Break Controller (PBC)
The PC break controller (PBC) provides functions that simplify program debugging. Using these
functions, it is easy to create a self-monitoring debugger, enabling programs to be debugged with
the chip alone, without using an in-circuit emulator. A block diagram of the PC break controller is
shown in figure 6.1.
6.1
Features
• Two break channels (A and B)
• 24-bit break address
Bit masking possible
• Four types of break compare conditions
Instruction fetch
data read
data write
data read/write
• Bus master
Either CPU or CPU/DTC can be selected
• The timing of PC break exception handling after the occurrence of a break condition is as
follows:
Immediately before execution of the instruction fetched at the set address (instruction
fetch)
Immediately after execution of the instruction that accesses data at the set address (data
access)
• Module stop mode can be set
PBC0000A_000020020300
Rev. 1.0, 09/02, page 85 of 568
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