Figure 15.8 Detailed Description Of One Bit; Table 15.2 Limits For The Settable Value - Hitachi H8S/2628 Hardware Manual

SYNC_SEG
1 time quanta
SYNC_SEG is a segment for establishing the synchronization of nodes on the CAN bus. Normal
bit edge transitions occur in this segment. PRSEG is a segment for compensating for the physical
delay between networks. PHSEG1 is a buffer segment for correcting phase drift (positive). This
segment is extended when synchronization (resynchronization) is established. PHSEG2 is a buffer
segment for correcting phase drift (negative). This segment is shortened when synchronization
(resynchronization) is established. Limits on the settable value (TSEG1, TSEG2, BRP, sample
point, and SJW) are shown in table 15.2.

Table 15.2 Limits for the Settable Value

Name
Time segment 1
Time segment 2
Baud rate prescaler
Bit sample point
Re-synchronization jump width
Notes: 1. SJW is stipulated in the CAN specifications:
3 ≥ SJW ≥ 0
2. The minimum value of TSEG2 is stipulated in the CAN specifications:
TSEG2 ≥ SJW
3. The minimum value of TSEG1 is stipulated in the CAN specifications:
TSEG1 > TSEG2
1-bit time (8–25 time quanta)
PRSEG
Time segment 1 (TSEG1)
2–16 time quanta

Figure 15.8 Detailed Description of One Bit

Abbreviation
TSEG1
TSEG2
BRP
BSP
SJW*
PHSEG1
Time segment 2
Min. Value
B'0011*
3
B'001*
B'000000
B'0
1
B'00
Rev. 1.0, 09/02, page 387 of 568
PHSEG2
(TSEG2)
Max. Value
2
B'1111
B'111
B'111111
B'1
B'11