Operation Timing; Tcnt Incrementation Timing; Figure 11.2 Example Of Pulse Output; Figure 11.3 Count Timing For Internal Clock Input - Hitachi H8S/2628 Hardware Manual

H'FF
TCORA
TCORB
H'00
TMO
11.5

Operation Timing

11.5.1

TCNT Incrementation Timing

Figure 11.3 shows the TCNT count timing with internal clock source. Figure 11.4 shows the
TCNT incrementation timing with external clock source. The pulse width of the external clock for
incrementation at signal edge must be at least 1.5 system clock (φ) periods, and at least 2.5 states
for incrementation at both edges. The counter will not increment correctly if the pulse width is less
than these values.
φ
Internal clock
TCNT input
clock
TCNT
Rev. 1.0, 09/03, page 252 of 568
TCNT

Figure 11.2 Example of Pulse Output

N – 1

Figure 11.3 Count Timing for Internal Clock Input

Counter clear
N N + 1