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HCAN sleep mode is entered by setting the HCAN sleep mode bit (MCR5) to 1 in the master
control register (MCR). If the CAN bus is operating, the transition to HCAN sleep mode is
delayed until the bus becomes idle.
Either of the following methods of clearing HCAN sleep mode can be selected:
• Clearing by software
• Clearing by CAN bus operation
In order to re-enter CAN bus communication enabled state, eleven recessive bits must be received
after HCAN sleep mode was cleared.
Clearing by software: HCAN sleep mode is cleared by writing a 0 to MCR5 from the CPU.
Clearing by CAN bus operation: The cancellation method is selected by the MCR7 bit setting in
MCR. Clearing by CAN bus operation occurs automatically when the CAN bus performs an
operation and this change is detected. In this case, the first message is not stored in a mailbox;
messages will be received normally from the second message onward. When a change is detected
on the CAN bus in HCAN sleep mode, the bus operation interrupt flag (IRR12) is set in the
interrupt register (IRR). If the bus interrupt mask (IMR12) in the interrupt mask register (IMR) is
set to enable interrupts at this time, an interrupt can be sent to the CPU.
Rev. 1.0, 09/02, page 398 of 568
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